METHOD AND APPARATUS FOR MINIMIZING SKEW BETWEEN SIGNALS

• US 20110221497A1
• Filed: 02/01/2011
• Published: 09/15/2011
• Est. Priority Date: 03/09/2006
• Status: Active Grant

• Current Assignee: Adam J. Wright, Chiakang Sung, Eric Choong-Yin Chang, Joseph Huang, Peter Boyle, Yan Chong
• Original Assignee: Adam J. Wright, Chiakang Sung, Eric Choong-Yin Chang, Joseph Huang, Peter Boyle, Yan Chong
• Inventors: Boyle, Peter, Chong, Yan, Wright, Adam J., Chang, Eric Choong-Yin, Sung, Chiakang, Huang, Joseph
• Granted Patent: US 8,779,754 B2
• Time in Patent Office: Days
• US Class Current: 327/161
• CPC Class Codes: G01R 31/3016 Delay or race condition test, e.g. race hazard test
• CPC Class Codes: G01R 31/31725 Timing aspects, e.g. clock distribution, skew, propagation delay for tester hardware G01R31/31937
• CPC Class Codes: G01R 31/318516 Test of programmable logic devices [PLDs]
• CPC Class Codes: H03K 5/135 by the use of time reference signals, e.g. clock signals
• CPC Class Codes: H03K 5/14 by the use of delay lines H03K5/133 takes precedence
• CPC Class Codes: H03K 5/1504 using a chain of active delay devices H03K5/15053 takes precedence

Abstract

Delay associated with each of two signals along respective transmission paths is accurately measured using a delay measurement circuit that is fabricated in situ on the actual device where the circuitry for propagating the two signals is fabricated. Thus, the measured delay associated with each of the two signals is subject to the same fabrication-dependent attributes that affect the actual circuitry through which the two signals will be propagated during operation of the device. The skew between the two signals is quantified as the difference in the measured delays. Coarse and fine delay modules are defined within the transmission path of each of the two signals. Based on the measured skew between the two signals, the coarse and fine delay modules are appropriately set to compensate for the skew. The appropriately settings for the coarse and fine delay modules can be stored in non-volatile memory elements.

Claims

1. A signal delay measurement circuit, comprising:

an input register defined to receive a test data signal and output the test data signal in accordance with a test clock signal;

an output register defined to receive a delayed version of the test data signal and output the delayed version of the test data signal in accordance with a delayed version of the test clock signal;

an emulation module connected between the input register and the output register, the emulation module defined to emulate an actual signal transmission path for which signal delay is to be measured, the emulation module defined to introduce signal delay in the test data signal as the test data signal is transmitted from the input register to arrive at the output register as the delayed version of the test data signal; and

a delay chain defined to introduce a controllable amount of signal delay in the test clock signal to generate the delayed version of the test clock signal.

2. A signal delay measurement circuit as recited in claim 1, wherein each of the input and output registers is defined as a flip-flop.

3. A signal delay measurement circuit as recited in claim 1, wherein the actual signal transmission path for which the emulation module is defined is either a data signal path of a memory controller interface or a data strobe signal path of the memory controller interface.

4. A signal delay measurement circuit as recited in claim 1, wherein a total amount of signal delay to be introduced by the delay chain represents a signal delay between arrival of the test clock signal at the input register and arrival of the delayed version of the test clock signal at the output register.

5. A signal delay measurement circuit as recited in claim 1, wherein the delay chain includes a number of serially connected delay elements, an output node of each serially connected delay element connected to a respective input of a multiplexer, the multiplexer defined to pass through one of its inputs as the delayed version of the test clock signal in accordance with a delay select signal.

6. A signal delay measurement circuit as recited in claim 5, wherein the delay select signal is controllable such that the delayed version of the test clock signal can be set to correspond to a signal present at the output node of a particular delay element within the delay chain.

7. A signal delay measurement circuit as recited in claim 5, wherein the serially connected delay elements include a first coarse delay element followed by a number of fine delay elements.

8. A signal delay measurement circuit as recited in claim 1, wherein the signal delay measurement circuit is configured as a fine delay element calibration circuit having the emulation module defined as a coarse delay element and the delay chain defined to include a number of serially connected fine delay elements, an output node of each serially connected fine delay element connected to a respective input of a multiplexer, the multiplexer defined to pass through one of its inputs as the delayed version of the test clock signal in accordance with a delay select signal.

9. A delay element calibration circuit, comprising:

an input register defined to receive a test data signal and output the test data signal in accordance with a test clock signal, wherein a period of the test clock signal is adjustable;

an output register defined to receive a delayed version of the test data signal and output the delayed version of the test data signal in accordance with the test clock signal; and

a chain of delay elements connected between the input register and the output register, the chain of delay elements defined to introduce signal delay in the test data signal as the test data signal is transmitted from the input register to arrive at the output register as the delayed version of the test data signal.

10. A delay element calibration circuit as recited in claim 9, wherein each of the input and output registers is defined as a flip-flop.

11. A delay element calibration circuit as recited in claim 9, wherein a total amount of signal delay to be introduced by the chain of delay elements represents a total amount of signal delay from an output port of the input register to an input port of the output register.

12. A delay element calibration circuit as recited in claim 9, wherein the chain of delay elements is defined to provide a total signal delay that is larger than a minimum achievable period of the test clock signal.

13. A delay element calibration circuit as recited in claim 9, wherein the chain of delay elements includes a number of serially connected delay elements, each of the number of serially connected delay elements defined to provide a substantially equivalent amount of signal delay.

14. A delay element calibration circuit as recited in claim 9, further comprising:

a phase lock loop circuit defined to generate the test clock signal, the phase lock loop circuit defined to enable discrete adjustment of the period of the test clock signal.

15. A method for minimizing skew between two signals, comprising:

calibrating a coarse delay element;

calibrating a fine delay element;

measuring signal delay associated with a first signal using the calibrated coarse and fine delay elements;

measuring signal delay associated with a second signal using the calibrated coarse and fine delay elements;

determining a skew between the first and second signals as a difference between the measured signal delay associated with the first signal and the measured signal delay associated with the second signal;

determining settings for coarse and fine delay modules to minimize the determined skew between the first and second signals, wherein the coarse and fine delay modules implement a selectable number of the coarse and fine delay elements respectively; and

storing the determined settings for the coarse and fine delay modules in non-volatile memory.

16. A method for minimizing skew between two signals as recited in claim 15, wherein calibration of either the coarse delay element or the fine delay element is performed using a calibration circuit that establishes a signal racing condition between a test clock signal of adjustable period and a test data signal.

17. A method for minimizing skew between two signals as recited in claim 16, wherein the calibration circuit is operated to race the test data signal against the test clock signal between a first register and a second register, the test data signal being transmitted through a fixed number of delay elements, the period of the test clock signal being incrementally increased until the second register catches the test data signal, a signal delay provided by an individual delay element being calibrated as the period of the test clock signal divided by the number of delay elements.

18. A method for minimizing skew between two signals as recited in claim 15, wherein measuring of the signal delay associated with each of the first and second signals is performed using a delay measurement circuit that establishes a signal racing condition between a test clock signal and a test data signal, wherein the test clock signal is subjected to a controllable amount of signal delay, and the test data signal is transmitted through an emulation module defined to emulate an actual transmission path associated with either the first or second signal having its delay measured.

19. A method for minimizing skew between two signals as recited in claim 18, wherein the delay measurement circuit is operated to race the test data signal against the test clock signal between a first register and a second register, the controllable amount of signal delay in the test clock signal being incrementally increased until the second register catches the test data signal, the signal delay provided by emulation module being approximately equal to the amount of signal delay in the test clock signal when the second register catches the test data signal.

20. A method for minimizing skew between two signals as recited in claim 15, wherein the delay present in the first signal is controllable by a first coarse delay module and a first fine delay module, and the delay in the second signal is controllable by a second coarse delay module and a second fine delay module.