METHOD AND APPARATUS FOR ADAPTING A VARIABLE IMPEDANCE NETWORK

• US 20110227666A1
• Filed: 03/22/2010
• Published: 09/22/2011
• Est. Priority Date: 03/22/2010
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Paratek Microwave Incorporated (Blackberry Limited)
• Inventors: MANSSEN, KEITH R., GREENE, MATTHEW R.
• Granted Patent: US 8,803,631 B2
• Time in Patent Office: Days
• US Class Current: 333/32
• CPC Class Codes: H03H 5/12 with at least one voltage- or current-dependent element
• CPC Class Codes: H03H 7/004 Capacitive coupling circuits not otherwise provided for
• CPC Class Codes: H03H 7/38 Impedance-matching networks
• CPC Class Codes: H03H 7/40 Automatic matching of load impedance to source impedance
• CPC Class Codes: H03K 17/56 by the use, as active elements, of semiconductor devices using diodes H03K17/74

Abstract

The present disclosure may include, for example, a tunable capacitor having a decoder for generating a plurality of control signals, and an array of tunable switched capacitors comprising a plurality of fixed capacitors coupled to a plurality of switches. The plurality of switches can be controlled by the plurality of control signals to manage a tunable range of reactance of the array of tunable switched capacitors. Additionally, the array of tunable switched capacitors is adapted to have non-uniform quality (Q) factors. Additional embodiments are disclosed.

Claims

1. A tunable capacitor, comprising:

a decoder for generating a plurality of control signals;

an array of tunable switched capacitors comprising a plurality of fixed capacitors coupled to a plurality of switches;

wherein the plurality of switches are controlled by the plurality of control signals to manage a tunable range of reactance of the array of tunable switched capacitors; and

wherein the array of tunable switched capacitors is adapted to have non-uniform quality (Q) factors.

2. The tunable capacitor of claim 1, wherein each of the switches are adapted to have a parasitic resistance which results in the non-uniform Q factors of the array of tunable switched capacitors.

3. The tunable capacitor of claim 2, wherein at least one of the switches comprises one of a plurality of semiconductor switches or a plurality of micro-electro-mechanical systems (MEMS) switches, and wherein a scaling factor of the plurality of semiconductor switches or the plurality of MEMS switches results in the non-uniform Q factors of the array of tunable switched capacitors.

4. The tunable capacitor of claim 3, wherein the scaling factor comprises combining switches in parallel or widening a conducting channel of such switches.

5. The tunable capacitor of claim 1, wherein at least a portion of the array of tunable switched capacitors is contained on a die.

6. The tunable capacitor of claim 5, wherein one of the plurality of fixed capacitors is optionally coupled to the array of tunable switched capacitors to reduce an aggregate parasitic capacitance of the array of tunable switched capacitors.

7. The tunable capacitor of claim 6, wherein one end of the optionally coupled fixed capacitor is coupled to a first external port of the die, wherein a portion of the array of tunable switched capacitors is coupled to a second external port of the die, and wherein the optionally coupled fixed capacitor is coupable to the array of tunable switched capacitors by way of the first and second external ports.

8. The tunable capacitor of claim 5, wherein the optionally coupled fixed capacitor is located externally to the die, wherein one of the plurality of switches is coupled to a first external port of the die, wherein a portion of the array of tunable switched capacitors is coupled to a second external port of the die, and wherein the optionally coupled fixed capacitor is coupable to the array of tunable switched capacitors by way of the first and second external ports.

9. The tunable capacitor of claim 1, wherein the plurality of fixed capacitors comprise capacitive values conforming to a binary sequence.

10. The tunable capacitor of claim 1, wherein the plurality of fixed capacitors comprise capacitive values conforming to a non-binary sequence.

11. The tunable capacitor of claim 1, wherein the decoder is adapted to receive data over a serial port to generate the plurality of control signals.

12. The tunable capacitor of claim 1, wherein a plurality of the tunable capacitors is utilized in a variable matching network.

13. The tunable capacitor of claim 12, wherein the variable matching network comprises a plurality of ports to support a plurality of matching network topologies comprising one of a “

Tee”

topology, a “

Pi”

topology, an “

L”

topology, or a combination thereof.

14. The tunable capacitor of claim 12, wherein the variable matching network is configurable as a high band or low band matching network.

15. A variable matching network, comprising:

a plurality of tunable capacitors contained on a single die;

wherein the single die has a plurality of ports coupled to portions of the plurality of tunable capacitors; and

wherein the variable matching network is configurable in a plurality of topologies by way of the plurality of ports.

16. The variable matching network of claim 15, wherein each of the plurality of tunable capacitors comprise an array of tunable switched capacitors adapted to have non-uniform quality (Q) factors.

17. The variable matching network of claim 16, wherein the array of tunable switched capacitors comprises a plurality of fixed capacitors coupled to a plurality of switches.

18. The variable matching network of claim 17, wherein the plurality of switches are controlled by a plurality of control signals to manage a tunable range of reactance of the array of tunable switched capacitors.

19. The variable matching network of claim 17, wherein each of the switches are adapted to have a parasitic resistance which results in a non-uniform Q factors of the array of tunable switched capacitors.

20. The variable matching network of claim 17, wherein at least one of the switches comprises one of a plurality of semiconductor switches or a plurality of micro-electro-mechanical systems (MEMS) switches, and wherein a scaling factor of the plurality of semiconductor switches or the plurality of MEMS switches results in the non-uniform Q factors of the array of tunable switched capacitors.

21. The variable matching network of claim 20, wherein the scaling factor comprises combining switches in parallel or widening a conducting channel of such switches.

22. The variable matching network of claim 15, wherein the plurality of tunable capacitors comprises a plurality of capacitors each having a tunable dielectric constant.

23. The variable matching network of claim 15, wherein the plurality of topologies comprise at least two of a “

Tee”

topology, a “

Pi”

topology, an “

L”

topology, or a combination thereof.

24. The variable matching network of claim 15, comprising an external fixed capacitor coupled to one of the plurality of tunable capacitors to raise a tuning range of the variable matching network.

25. The variable matching network of claim 15, comprising a switch adapted to bypass a reactive element of the matching network.

26. The variable matching network of claim 25, wherein the switch is contain on or external to the single die, and wherein the reactive element corresponds to one of the plurality of tunable capacitors or one or more external reactive elements coupled to the variable matching network.

27. A device, comprising first and second variable capacitors within a single die with each end of said first and second variable capacitors having an accessible external port, wherein the first and second variable capacitors are adapted to be configured as a Tee, Pi or L circuit topology.

28. The device of claim 27, wherein the first and second variable capacitors comprise an array of tunable switched capacitors adapted to have non-uniform quality (Q) factors.

29. The device of claim 28, wherein the array of tunable switched capacitors comprises a plurality of fixed capacitors coupled to a plurality of switches.

30. The device of claim 29, wherein at least one of the switches comprises one of a plurality of semiconductor switches or a plurality of micro-electro-mechanical systems (MEMS) switches.

31. The device of claim 29, wherein the plurality of switches are scaled to reduce a size of the single integrated circuit by allowing non-uniform Q factors in the array of tunable switched capacitors.

32. The device of claim 27, wherein a plurality of the devices are utilized in a corresponding plurality of RF paths.

33. The device of claim 32, wherein the plurality RF paths correspond to at least one of high or low band RF paths.

34. The device of claim 33, wherein the high or low band RF paths are switchable among a plurality of ports of the single die.

35. A method, comprising causing an array of tunable switched reactive elements to adapt to a variable load impedance, wherein the array of tunable switched reactive elements is configured to have non-uniform quality (Q) factors.

36. The method of claim 35, wherein the array of tunable switched reactive elements comprises one of one or more fixed capacitors coupled to one or more switches, one or more fixed inductors coupled to one or more switches, or combinations thereof.

37. The method of claim 36, wherein at least one of the switches comprises one of a plurality of semiconductor switches or a plurality of micro-electro-mechanical systems (MEMS) switches, and wherein a scaling factor of the plurality of semiconductor switches or the plurality of MEMS switches results in the non-uniform Q factors of the array of tunable switched reactive elements.

38. A tunable capacitor on a die, comprising:

a decoder for generating a plurality of control signals;

an array of tunable switched capacitors comprising a plurality of fixed capacitors coupled to a plurality of switches;

wherein the plurality of switches are controlled by the plurality of control signals to manage a tunable range of reactance of the array of tunable switched capacitors;

wherein one of the plurality of fixed capacitors is optionally coupled to the array to reduce an aggregate parasitic capacitance of the array of tunable switched capacitors; and

wherein the array of tunable switched capacitors is adapted to have uniform quality (Q) factors.

39. The tunable capacitor of claim 38, wherein one end of the optionally coupled fixed capacitor is coupled to a first external port of the die, wherein a portion of the array of tunable switched capacitors is coupled to a second external port of the die, and wherein the optionally coupled fixed capacitor is coupable to the array of tunable switched capacitors by way of the first and second external ports.

40. The tunable capacitor of claim 38, wherein the optionally coupled fixed capacitor is located externally to the die, wherein one of the plurality of switches is coupled to a first external port of the die, wherein a portion of the array of tunable switched capacitors is coupled to a second external port of the die, and wherein the optionally coupled fixed capacitor is coupable to the array of tunable switched capacitors by way of the first and second external ports.