METHODS AND APPARATUS FOR PRIORITY INITIALIZATION OF A SECOND PROCESSOR

• US 20110231640A1
• Filed: 09/21/2010
• Published: 09/22/2011
• Est. Priority Date: 11/13/2009
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Avadhanam, Phani B.
• Granted Patent: US 8,938,609 B2
• Time in Patent Office: Days
• US Class Current: 713/2
• CPC Class Codes: G06F 9/4403 Processor initialisation
• CPC Class Codes: G06F 9/4405 Initialisation of multiprocessor systems

Abstract

Methods and systems provide for activating a second processor by a first processor in a dual processor device early within an initialization routine to enable the second processor to help complete initialization operations. The first processor may prepare a second processor chip for start up, configure the second chip'"'"'s pins, program the second processor, download a firmware image on the second processor, and initiate operations on the second processor. By performing this initialization early within the initialization routine, the second processor can assist in the initialization routine.

Claims

1. A method for activating a second processor by a first processor within an initialization routine, comprising:

preparing a second chip for operation, the second chip comprising the second processor;

configuring the second chip'"'"'s pins;

programming the second processor by the first processor; and

downloading and running a firmware image on the second processor,

wherein the second processor is activated early enough within the initialization routine to assist in the initialization routine.

2. The method of claim 1, wherein preparing a second chip comprises:

disabling interrupt service routines of the second chip;

turning on the general purpose input/output pins between the first chip and the second chip;

making sure the second chip is powered down; and

waiting for at least 300 microseconds.

3. The method of claim 2, wherein preparing a second chip further comprises:

setting up voltage rails for a peripheral device connected to the second chip.

4. The method of claim 2, wherein configuring the second chip'"'"'s pins comprises:

configuring the second chip'"'"'s mode control pins;

toggling the second chip'"'"'s reset pin further comprises; and

waiting for at least 20 milliseconds.

5. The method of claim 1, wherein programming the second processor by the first processor comprises:

performing a second chip detection algorithm;

programming phase locked loops;

programming clock control registers;

enabling the second processor to be driven by a core clock;

programming the top level logic;

resetting and programming a sleep controller block with initial values; and

initializing second processor clock controls.

6. The method of claim 1, wherein preparing a second chip comprises:

disabling interrupt service routines of the second chip;

turning on general purpose input/output pins between the first chip and the second chip;

setting up voltage rails for a peripheral device connected to the second chip;

making sure the second chip is powered down; and

waiting for at least 300 microseconds,

wherein configuring the second chip'"'"'s pins comprises;

configuring the second chip'"'"'s mode control pins;

toggling the second chip'"'"'s reset pin further comprises; and

waiting for at least 20 milliseconds, and

wherein programming the second processor by the first processor comprises;

performing a second chip detection algorithm;

programming phase locked loops;

programming clock control registers;

enabling the second processor to be driven by a core clock;

programming the top level logic;

resetting and programming a sleep controller block with initial values; and

initializing second processor clock controls.

7. The method of claim 6, wherein the second processor is a DSP, the second chip is a receiver chip, and the first chip is a modem chip.

8. An electronic device, comprising:

a first processor; and

a second processor coupled to the first processor,

wherein the first and second processors are configured with processor-executable instructions to perform operations comprising;

preparing a second chip for operation, the second chip comprising the second processor;

configuring the second chip'"'"'s pins;

programming the second processor by the first processor; and

downloading and running a firmware image on the second processor,

wherein the second processor is activated early enough within an initialization routine to assist in the initialization routine.

9. The electronic device of claim 8, wherein the first and second processors are configured with processor-executable instructions to perform operations such that preparing a second chip comprises:

disabling interrupt service routines of the second chip;

turning on the general purpose input/output pins between the first chip and the second chip;

making sure the second chip is powered down; and

waiting for at least 300 microseconds.

10. The electronic device of claim 9, wherein the first and second processors are configured with processor-executable instructions to perform operations such that preparing a second chip further comprises:

setting up voltage rails for a peripheral device connected to the second chip.

11. The electronic device of claim 9, wherein the first and second processors are configured with processor-executable instructions to perform operations such that configuring the second chip'"'"'s pins comprises:

configuring the second chip'"'"'s mode control pins;

toggling the second chip'"'"'s reset pin further comprises; and

waiting for at least 20 milliseconds.

12. The electronic device of claim 8, wherein the first and second processors are configured with processor-executable instructions to perform operations such that programming the second processor by the first processor comprises:

performing a second chip detection algorithm;

programming phase locked loops;

programming clock control registers;

enabling the second processor to be driven by a core clock;

programming the top level logic;

resetting and programming a sleep controller block with initial values; and

initializing second processor clock controls.

13. The electronic device of claim 8, wherein the first and second processors are configured with processor-executable instructions to perform operations such that preparing a second chip comprises:

disabling interrupt service routines of the second chip;

turning on general purpose input/output pins between the first chip and the second chip;

setting up voltage rails for a peripheral device connected to the second chip;

making sure the second chip is powered down; and

waiting for at least 300 microseconds,

wherein configuring the second chip'"'"'s pins comprises;

configuring the second chip'"'"'s mode control pins;

toggling the second chip'"'"'s reset pin further comprises; and

waiting for at least 20 milliseconds, and

wherein programming the second processor by the first processor comprises;

performing a second chip detection algorithm;

programming phase locked loops;

programming clock control registers;

enabling the second processor to be driven by a core clock;

programming the top level logic;

resetting and programming a sleep controller block with initial values; and

initializing second processor clock controls.

14. The electronic device of claim 13, wherein the second processor is a DSP, the second chip is a receiver chip, and the first chip is a modem chip.

15. A non-transitory processor-readable storage medium having stored thereon processor-executable instructions configured to cause a first processor and a second processor within a single electronic device to perform operations comprising:

preparing a second chip for operation, the second chip comprising the second processor;

configuring the second chip'"'"'s pins;

programming the second processor by the first processor; and

downloading and running a firmware image on the second processor,

wherein the second processor is activated early enough within an initialization routine to assist in the initialization routine.

16. The non-transitory processor-readable storage medium of claim 15, wherein the stored processor-executable instructions are configured to cause a first processor and a second processor within a single electronic device to perform operations such that preparing a second chip comprises:

disabling interrupt service routines of the second chip;

turning on the general purpose input/output pins between the first chip and the second chip;

making sure the second chip is powered down; and

waiting for at least 300 microseconds.

17. The non-transitory processor-readable storage medium of claim 16, wherein the stored processor-executable instructions are configured to cause a first processor and a second processor within a single electronic device to perform operations such that preparing a second chip further comprises:

setting up voltage rails for a peripheral device connected to the second chip.

18. The non-transitory processor-readable storage medium of claim 16, wherein the stored processor-executable instructions are configured to cause a first processor and a second processor within a single electronic device to perform operations such that configuring the second chip'"'"'s pins comprises:

configuring the second chip'"'"'s mode control pins;

toggling the second chip'"'"'s reset pin further comprises; and

waiting for at least 20 milliseconds.

19. The non-transitory processor-readable storage medium of claim 15 wherein the stored processor-executable instructions are configured to cause a first processor and a second processor within a single electronic device to perform operations such that programming the second processor by the first processor comprises:

performing a second chip detection algorithm;

programming phase locked loops;

programming clock control registers;

enabling the second processor to be driven by a core clock;

programming the top level logic;

resetting and programming a sleep controller block with initial values; and

initializing second processor clock controls.

20. The non-transitory processor-readable storage medium of claim 15, wherein the stored processor-executable instructions are configured to cause a first processor and a second processor within a single electronic device to perform operations such that preparing a second chip comprises:

disabling interrupt service routines of the second chip;

turning on general purpose input/output pins between the first chip and the second chip;

setting up voltage rails for a peripheral device connected to the second chip;

making sure the second chip is powered down; and

waiting for at least 300 microseconds,

wherein configuring the second chip'"'"'s pins comprises;

configuring the second chip'"'"'s mode control pins;

toggling the second chip'"'"'s reset pin further comprises; and

waiting for at least 20 milliseconds, and

wherein programming the second processor by the first processor comprises;

performing a second chip detection algorithm;

programming phase locked loops;

programming clock control registers;

enabling the second processor to be driven by a core clock;

programming the top level logic;

resetting and programming a sleep controller block with initial values; and

initializing second processor clock controls.

21. The non-transitory processor-readable storage medium of claim 20 wherein the second processor is a DSP, the second chip is a receiver chip, and the first chip is a modem chip.

22. An electronic device, comprising:

a first processor;

a second processor coupled to the first processor;

means for preparing a second chip for operation, the second chip comprising the second processor;

means for configuring the second chip'"'"'s pins;

means for programming the second processor by the first processor; and

means for downloading and running a firmware image on the second processor,

wherein the second processor is activated early enough within an initialization routine to assist in the initialization routine.

23. The electronic device of claim 22, wherein means for preparing a second chip comprises:

means for disabling interrupt service routines of the second chip;

means for turning on the general purpose input/output pins between the first chip and the second chip;

means for making sure the second chip is powered down; and

means for waiting for at least 300 microseconds.

24. The electronic device of claim 23, wherein means for preparing a second chip further comprises:

means for setting up voltage rails for a peripheral device connected to the second chip.

25. The electronic device of claim 23, wherein means for configuring the second chip'"'"'s pins comprises:

means for configuring the second chip'"'"'s mode control pins;

means for toggling the second chip'"'"'s reset pin further comprises; and

means for waiting for at least 20 milliseconds.

26. The electronic device of claim 22, wherein means for programming the second processor by the first processor comprises:

means for performing a second chip detection algorithm;

means for programming phase locked loops;

means for programming clock control registers;

means for enabling the second processor to be driven by a core clock;

means for programming the top level logic;

means for resetting and programming a sleep controller block with initial values; and

means for initializing second processor clock controls.

27. The electronic device of claim 22, wherein means for preparing a second chip comprises:

means for disabling interrupt service routines of the second chip;

means for turning on general purpose input/output pins between the first chip and the second chip;

means for setting up voltage rails for a peripheral device connected to the second chip;

means for making sure the second chip is powered down; and

means for waiting for at least 300 microseconds,

wherein means for configuring the second chip'"'"'s pins comprises;

means for configuring the second chip'"'"'s mode control pins;

means for toggling the second chip'"'"'s reset pin further comprises; and

means for waiting for at least 20 milliseconds, and

wherein means for programming the second processor by the first processor comprises;

means for performing a second chip detection algorithm;

means for programming phase locked loops;

means for programming clock control registers;

means for enabling the second processor to be driven by a core clock;

means for programming the top level logic;

means for resetting and programming a sleep controller block with initial values; and

means for initializing second processor clock controls.

28. The electronic device of claim 27, wherein the second processor is a DSP, the second chip is a receiver chip, and the first chip is a modem chip.