METHOD FOR MANUFACTURING A SEMICONDUCTOR SUBSTRATE

• US 20110241157A1
• Filed: 06/03/2010
• Published: 10/06/2011
• Est. Priority Date: 04/06/2010
• Status: Active Grant

• Current Assignee: Soitec S.A.
• Original Assignee: Soitec S.A.
• Inventors: Mazure, Carlos, Nguyen, Bich-Yen, Bourdelle, Konstantin, Ferrant, Richard
• Granted Patent: US 9,035,474 B2
• Time in Patent Office: Days
• US Class Current: 257/506
• CPC Class Codes: H01L 21/187 by direct bonding
• CPC Class Codes: H01L 21/2007 Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer H01L21/2011 takes precedence; bonding of semiconductor wafers to semiconductor wafers for junction formation H01L21/187
• CPC Class Codes: H01L 21/76251 using bonding techniques
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

Abstract

The invention relates to a method for manufacturing a semiconductor substrate, in particular a semiconductor-on-insulator substrate by providing a donor substrate and a handle substrate, forming a pattern of one or more doped regions typically inside the handle substrate, and then attaching such as by molecular bonding the donor and the handle substrate to obtain a donor-handle compound.

Claims

1. A method for manufacturing a semiconductor substrate which comprises:

providing a donor substrate and a handle substrate;

forming a pattern of one or more doped regions inside the handle substrate; and

attaching the donor and the handle substrates together to obtain a semiconductor substrate as a donor-handle combination.

2. The method of claim 1, wherein the donor and the handle substrates are attached together by molecular bonding, with one of the substrates including a surface layer of an insulator so that the donor-handle combination forms a semiconductor-on-insulator substrate.

3. The method of claim 2, which further comprises forming one or more alignment marks inside the handle substrate.

4. The method of claim 3, wherein the one or more alignment marks are formed by ion implantation.

5. The method of claim 3, wherein the one or more alignment marks comprise a non-dopant species.

6. The method of claim 5, wherein the non-dopant species is H, He, Ar, F, Ne, Xe or a combination thereof.

7. The method of claim 3, wherein the forming further comprises thermal annealing of the donor-handle combination.

8. The method of claim 1, wherein the pattern is formed by at least one ion implantation step for implanting the dopant.

9. The method of claim 8, wherein the dopant is phosphorus, arsenic, boron or a combination thereof.

10. The method of claim 8, wherein the at least one ion implantation step is followed by an annealing step.

11. The method of claim 1, which further comprises forming a screening layer by applying a screening oxide on the handle substrate prior to the forming of the pattern.

12. The method of claim 1, which further comprises, prior to the attaching of the substrates, forming a predetermined splitting area at a depth h inside the donor substrate and detaching a remainder of the donor substrate from the donor-handle combination at the predetermined splitting area after the attaching of the substrates.

13. The method of claim 1, which further comprises forming a dielectric layer or a combination of stacked layers comprising at least one dielectric layer on the donor substrate prior to the attaching of the substrates.

14. The method of claim 13, wherein the dielectric layer comprises an oxide and has a thickness of less than 200 nm or less than 100 nm.

15. The method of claim 1, wherein the pattern of one or more doped regions comprises one or more lines or one or more islands of dopants.

16. The method of claim 1, wherein the pattern of one or more doped regions comprises at least one well region or at least one back gate.

17. The method of claim 16, wherein both the at least one well region and at least one back gate are formed using the same mask.

18. A method for manufacturing a semiconductor substrate which comprises:

providing a donor substrate and a handle substrate;

forming one or more alignment marks inside the handle substrate; and

attaching the donor and the handle substrates together to obtain a semiconductor substrate as a donor-handle combination.

19. A semiconductor substrate comprising a donor-handle combination of a donor substrate and a handle substrate with one or more alignment marks or a pattern of one or more doped regions inside the handle substrate.

20. The semiconductor substrate of claim 19, further comprising a predetermined splitting area at a depth h inside the donor substrate.

21. A semiconductor-on-insulator substrate comprising a substrate layer, a semiconductor layer and a dielectric layer between the substrate layer and the semiconductor layer, wherein the substrate layer comprises one or more alignment marks or a pattern of one or more doped regions.

22. The semiconductor-on-insulator substrate according to claim 21, wherein the dielectric layer comprises an oxide and the pattern of one or more doped regions does not extend into the semiconductor layer or the dielectric layer.