Electronic Device and Manufacturing Method

• US 20110241218A1
• Filed: 03/31/2010
• Published: 10/06/2011
• Est. Priority Date: 03/31/2010
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Hess, Reinhard, Sezi, Recai, Meyer, Thorsten, Leuschner, Rainer, Ofner, Gerald
• Granted Patent: US 8,183,696 B2
• Time in Patent Office: Days
• US Class Current: 257/774
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 2224/211 Disposition
• CPC Class Codes: H01L 2224/221 Disposition
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/1035 the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1052 Wire or wire-like electrical connections
• CPC Class Codes: H01L 2225/107 Indirect electrical connections, e.g. via an interposer, a flexible substrate, using TAB printed circuits H05K1/00
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01068 : Erbium [Er]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13062 : Junction field-effect transistor [JFET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

A semiconductor package includes a semiconductor chip, an encapsulant embedding the semiconductor chip, first contact pads on a first main face of the semiconductor package and second contact pads on a second main face of the semiconductor package opposite to the first main face. The diameter d in micrometers of an exposed contact pad area of the second contact pads satisfies d≧(8/25)x+142 μm, wherein x is the pitch of the second contact pads in micrometers.

Claims

1. a semiconductor package, comprising:

a semiconductor chip;

an encapsulant embedding the semiconductor chip;

first contact pads on a first main face of the semiconductor package; and

second contact pads on a second main face of the semiconductor package opposite the first main face, wherein a diameter d in micrometers of an exposed contact pad area of the second contact pads satisfies d≧

(8/25)x+142 μ

m, wherein x is a pitch of the second contact pads in micrometers.

2. The semiconductor package of claim 1, wherein the first contact pads form package terminals arranged to be bonded to a board.

3. The semiconductor package of claim 1, wherein the second contact pads form package terminals arranged to be bonded to another semiconductor package.

4. The semiconductor package of claim 1, wherein the exposed contact pad area of the second contact pads is defined by an opening in a solder mask layer overlying a metal layer forming the second contact pads.

5. The semiconductor package of claim 1, wherein the exposed contact pad area of the second contact pads is defined by lateral dimensions of a metal layer forming the second contact pads.

6. The semiconductor package of claim 1, wherein the diameter d in micrometers satisfies d≦

(8/25)x+172 μ

m.

7. The semiconductor package of claim 1, wherein the pitch is x=400 micrometers and the diameter is d≧

260 micrometers.

8. The semiconductor package of claim 1, wherein the pitch is x=500 micrometers and the diameter is d≧

300 micrometers.

9. The semiconductor package of claim 1, wherein the pitch is x=650 micrometers and the diameter is d≧

340 micrometers.

10. The semiconductor package of claim 1, further comprising:

an element having a conductive via, the conductive via extending from the first main face of the semiconductor package to a metal layer forming the second contact pads.

11. The semiconductor package of claim 10, wherein the element is made of an insulating material.

12. A package-on-package device, comprising:

a first semiconductor package comprising a first semiconductor chip, an encapsulant embedding the first semiconductor chip, first contact pads on a first main face of the first semiconductor package and second contact pads on a second main face of the first semiconductor package opposite the first main face; and

a second semiconductor package comprising a second semiconductor chip, an encapsulant embedding the second semiconductor chip and third contact pads on a first main face of the second semiconductor package,

wherein the first main face of the second semiconductor package faces the second main face of the first semiconductor package and the second contact pads are electrically connected to the third contact pads via solder interconnects, and

wherein a diameter d in micrometers of an exposed contact pad area of the second contact pads satisfies d≧

(8/25)x+142 μ

m, wherein x is a pitch of the second contact pads in micrometers.

13. The package-on-package device of claim 12, wherein the exposed contact pad area of the second contact pads is defined by an opening in a solder mask layer overlying a metal layer forming the second contact pads.

14. The package-on-package device of claim 12, wherein the exposed contact pad area of the second contact pads is defined by lateral dimensions of a metal layer forming the second contact pads.

15. The package-on-package device of claim 12, wherein the diameter d in micrometers satisfies d≦

(8/25)x+172 μ

m.

16. The package-on-package device of claim 12, wherein the first semiconductor chip is a logic circuit, a power circuit or an optical circuit.

17. The package-on-package device of claim 12, wherein the second semiconductor chip is a memory chip.

18. The package-on-package device of claim 12, wherein a spacing between the first main face of the second semiconductor package and the second main face of the first semiconductor package has a dimension that varies by more than 8 micrometers across a lateral extension of the spacing.

19. The package-on-package device of claim 12, wherein the first main face of the second semiconductor package has a warpage height of at least 8 micrometers across a lateral extension of the first main face.

20. The package-on-package device of claim 12, wherein the second main face of the first semiconductor package has a warpage height of at least 8 micrometers across a lateral extension of the second main face.

21. A method of manufacturing a semiconductor package, the method comprising:

placing at least two semiconductor chips on a carrier;

covering the at least two semiconductor chips with a molding material to form an encapsulant;

removing the carrier from the at least two semiconductor chips;

forming a number of contact pads on a surface of the encapsulant facing away from the surface of the encapsulant which is defined by the carrier, a diameter d in micrometers of an exposed area of each contact pad satisfying d≧

(8/25)x+142 μ

m, wherein x is a pitch of the contact pads in micrometers; and

singulating the at least two semiconductor chips.

22. The method of claim 21, further comprising:

placing at least one element having a conductive via next to at least one of the semiconductor chips.

23. A method of manufacturing a package-on-package device, the method comprising:

providing a mounting platform;

placing a first semiconductor package comprising a first semiconductor chip, an encapsulant embedding the first semiconductor chip, first contact pads on a first main face of the first semiconductor package and second contact pads on a second main face of the first semiconductor package opposite to the first main face on the mounting platform;

placing a second semiconductor package comprising a second semiconductor chip, an encapsulant embedding the second semiconductor chip and third contact pads on a first main face of the second semiconductor package on the first semiconductor package, wherein the first main face of the second semiconductor package faces the second main face of the first semiconductor package; and

reflow soldering to electrically connect the second contact pads to the third contact pads and the first contact pads to the mounting platform,

wherein a diameter d in micrometers of an exposed contact pad area of the second contact pads satisfies d≧

(8/25)x+142 μ

m, wherein x is a pitch of the second contact pads in micrometers.