METHOD AND APPARATUS FOR OPERATIONAL-LEVEL FUNCTIONAL AND DEGRADATION FAULT ANALYSIS

• US 20110246831A1
• Filed: 04/02/2010
• Published: 10/06/2011
• Est. Priority Date: 04/02/2010
• Status: Active Grant

• Current Assignee: GM Global Technology Operations LLC (General Motors Company)
• Original Assignee: GM Global Technology Operations Incorporated (Motors Liquidation Co. GUC Trust)
• Inventors: Das, Dipankar, Chakrabarti, Partha P., Sinha, Purnendu
• Granted Patent: US 8,108,728 B2
• Time in Patent Office: Days
• US Class Current: 714/37
• CPC Class Codes: G06F 2117/02 Fault tolerance, e.g. for transient fault suppression
• CPC Class Codes: G06F 30/3323 using formal methods, e.g. equivalence checking or property checking

Abstract

An apparatus and method are provided for analyzing fault tolerance of a system, and performing “what if?” analysis for various fault-tolerant system design options. The fault tolerance analysis approach handles logical failures and quality faults emanating from loss of precision in signal values. The method can detect quality faults, which can allow systems to be built which are resilient to precision losses. Two analysis steps are provided, one static and another simulation-based, which are used in tandem to check the fault tolerance of an automotive or other system. While a simulation-based method checks fault-resilience under specific test cases and fault-scenarios, the static analysis method quickly checks all test cases and fault-scenarios. The static analysis method makes approximations while performing the analysis, and any fault detected is reproduced using the simulation-based method. All analysis operations are performed on operations-level behavioral models of the applications, thereby reducing the cost of analysis.

Claims

1. A method for analyzing the fault tolerance (FT) capability of a system, the method comprising:

recording, on tangible media that is accessible by a host machine, a set of calibrated FT requirements defining a functional specification for the system;

using the host machine to generate an operations-level model of the system;

automatically characterizing a behavior of a set of components of the system, as represented by the model, as a discrete lookup table (LUT); and

using the host machine to analyze the FT capability of the system via the discrete LUT and the functional specification;

wherein analyzing the FT capability of the system includes analyzing a predetermined set of logical failures and quality faults of the system.

2. The method of claim 1, further comprising:

recording an alternate design scenario for the system on the tangible media; and

automatically analyzing the alternate design scenario via the host machine using the LUT and the functional specification.

3. The method of claim 1, further comprising:

checking via the host machine, as a first set of steps, all possible combinations of inputs and fault-scenarios in the functional specification; and

checking via the host machine, as a second set of steps, an FT status of the system under a set of calibrated test cases and fault-scenarios using the LUT.

4. The method of claim 1, further comprising:

determining the presence of a violation of the FT requirements during the first set of steps; and

reproducing a set of system behavior leading to the violation in a second model.

5. The method of claim 1, further comprising:

storing the characterized quality behavior of the components in the LUT; and

processing the LUT using the host machine to determine the quality behavior of the system.

6. The method of claim 1, further comprising:

using at least one of a LUT-based simulation and a discrete LUT-based static analysis method to detect a counterexample; and

automatically reproducing the counterexample in the FT specification;

wherein the counterexample describes a set of fault values in different components of the set of components, with the fault values causing the system to behave in such a manner as to violate the FT requirements.

7. The method of claim 6, including using the LUT-based static analysis method, wherein the using LUT-based static analysis method includes using at least one of:

model checking, Boolean satisfiability solving, Satisfiability Modulo Theory solving, and search algorithms.

8. The method of claim 1, further comprising:

inputting each of a test case, a fault-scenario, and the fault tolerance requirement specifications into the host machine, wherein;

the fault-scenario is a set of triplets of the form of location, fault-type, and measure;

the location denotes a signal afflicted by the fault; and

the fault-type and measure denote the type and measure of error, respectively.

9. The method of claim 1, wherein the model includes a FT selection block, the method further comprising using the FT selection block to detect and select a non-faulty input, and to transfer the non-faulty input to an output of the FT selection block.

10. An apparatus adapted for analyzing the fault tolerance (FT) capabilities of a system, the apparatus comprising:

a host machine; and

tangible media accessible by the host machine, and on which is recorded a functional specification defining a formalized set of fault tolerance (FT) requirements;

wherein the host machine is adapted for;

generating an operations-level model of the system using the host machine;

characterizing the behavior of a set of components of the model as a discrete lookup table (LUT); and

analyzing the FT capability of the system using the discrete LUT and the functional specification, wherein analyzing the FT capability includes analyzing a predetermined set of logical failures and quality faults of the system.

11. The apparatus of claim 10, further comprising an alternate design scenario recorded on the tangible media and accessible by the host machine, wherein the host machine is adapted for automatically analyzing the alternate scenario using the LUT and the functional specification.

12. The apparatus of claim 10, wherein the host machine is configured for:

checking, as a first set of steps, all possible combinations of inputs and fault-scenarios in the functional specification; and

checking, as a second set of steps, an FT status of the system under a set of calibrated test cases and fault-scenarios using the LUTs.

13. The apparatus of claim 10, wherein the host machine is configured for:

determining the presence of a violation of the FT requirements during the first set of steps; and

reproducing a set of system behavior leading to the violation in a native operations-level model.

14. The apparatus of claim 10, wherein the host machine is configured for:

characterizing the quality behavior of individual electronic software and mechanical components of the system;

storing the characterized quality behavior in at least one of the LUTs; and

processing the stored information to determine the quality behavior of the system.

15. The apparatus of claim 10, wherein the host machine is configured for:

using at least one of a LUT-based simulation and a discrete LUT-based static analysis method to detect a counterexample; and

reproducing the counterexample in the operations-level model;

wherein the counterexample describes a set of fault values in different components of the system, the fault values causing the system to behave in such a manner as to violate the FT requirements.

16. The apparatus of claim 15, wherein the host machine is adapted for using the LUT-based static analysis method, and the LUT-based static analysis method includes at least one of:

model checking, Boolean satisfiability solving, Satisfiability Modulo Theory solving, and search algorithms.

17. The apparatus of claim 16, wherein the host machine is adapted for recording, on the tangible media, each of:

a test case, a fault-scenario, and the FT requirement specifications, and wherein;

the fault-scenario is a set of triplets of the form of location, fault-type, and measure;

the location denotes a signal afflicted by the fault; and

the fault-type and measure denote the type and measure of error, respectively.