CACHE-AWARE THREAD SCHEDULING IN MULTI-THREADED SYSTEMS

• US 20110246995A1
• Filed: 04/05/2010
• Published: 10/06/2011
• Est. Priority Date: 04/05/2010
• Status: Active Grant

• Current Assignee: Oracle International Corporation (Oracle Corporation)
• Original Assignee: Oracle International Corporation (Oracle Corporation)
• Inventors: Vengerov, David, Fedorova, Alexandra, Pusukuri, Kishore Kumar
• Granted Patent: US 8,533,719 B2
• Time in Patent Office: Days
• US Class Current: 718/103
• CPC Class Codes: G06F 9/5033 considering data affinity
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The disclosed embodiments provide a system that facilitates scheduling threads in a multi-threaded processor with multiple processor cores. During operation, the system executes a first thread in a processor core that is associated with a shared cache. During this execution, the system measures one or more metrics to characterize the first thread. Then, the system uses the characterization of the first thread and a characterization for a second, second thread to predict a performance impact that would occur if the second thread were to simultaneously execute in a second processor core that is also associated with the cache. If the predicted performance impact indicates that executing the second thread on the second processor core will improve performance for the multi-threaded processor, the system executes the second thread on the second processor core.

Claims

1. A method for predictively scheduling a thread in a multi-threaded processor, comprising:

executing a first thread in a processor core associated with a shared cache;

while executing the first thread, measuring one or more metrics to characterize the first thread;

using the characterization of the first thread and a characterization of a second thread to predict a performance impact associated with simultaneously executing the second thread in a second processor core which is associated with the cache; and

when the predicted performance impact indicates that executing the second thread on the second processor core will improve performance for the multi-threaded processor, executing the second thread on the second processor core.

2. The method of claim 1, wherein measuring one or more metrics includes measuring one or more of the following over a time interval:

the number of cycles elapsed per second for the processor core or the second processor core;

the average instructions executed per second by a given thread;

the average cache accesses per second for the given thread; and

the average cache misses per second for the given thread.

3. The method of claim 2, wherein characterizing the given thread involves using the measured metrics to determine whether the given thread is one or more of the following:

cache-intensive;

cache-sensitive; and

cache-insensitive.

4. The method of claim 3, wherein the method further comprises:

executing the second thread in a third processor core which is not associated with the cache;

executing a third thread in the second processor core;

measuring one or more metrics to characterize the second thread; and

measuring one or more metrics to characterize the third thread;

wherein predicting the performance impact involves using the characterization of the third thread and the characterization of the second thread in addition to the characterization of the first thread to determine whether migrating the second thread to the second processor core will improve performance for the multi-threaded processor.

5. The method of claim 4, wherein predicting the performance impact involves predicting a degradation in the average instructions executed per second for one or more of the following:

the first thread;

the second thread; and

the third thread.

6. The method of claim 5, where the method further comprises gathering data for thread characteristics and associated performance impacts by performing one or more of the following:

periodically migrating one or more threads between processor cores of the multi-threaded processor; and

opportunistically gathering data during normal multi-threaded execution in the multi-threaded processor.

7. The method of claim 6, wherein the method uses online thread characteristic and performance data to facilitate scheduling threads across processor cores.

8. The method of claim 6, wherein the method facilitates application-independent scheduling techniques that are self-managing across changing data sets, changing data access patterns, and changing user requests.

9. The method of claim 6, wherein the method further comprises:

using the gathered data as inputs to a forecasting system; and

using the forecasting system to predict the performance impact.

10. The method of claim 9, wherein the method further comprises using statistical feedback from measured metrics, thread characteristics and thread interactions to update a parameter of the forecasting system.

11. The method of claim 1, wherein improving performance for the chip multi-threaded processor involves one or more of the following:

improving the overall instruction throughput for the chip multi-threaded processor; and

reducing the power consumed by the chip multi-threaded processor while executing the threads.

12. The method of claim 1,

wherein a processor core of the multi-threaded processor can execute multiple threads simultaneously;

and

wherein the processor core and the second processor core are a single processor core that can simultaneously execute both the first thread and the second thread.

13. A non-transitory computer-readable storage medium storing instructions that when executed by a computer cause the computer to perform a method for predictively scheduling a thread in a multi-threaded processor, the method comprising:

executing a first thread in a processor core associated with a shared cache;

while executing the first thread, measuring one or more metrics to characterize the first thread;

using the characterization of the first thread and a characterization of a second thread to predict a performance impact associated with simultaneously executing the second thread in a second processor core which is associated with the cache; and

when the predicted performance impact indicates that executing the second thread on the second processor core will improve performance for the multi-threaded processor, executing the second thread on the second processor core.

14. The non-transitory computer-readable storage medium of claim 13, wherein measuring one or more metrics includes measuring one or more of the following over a time interval:

the number of cycles elapsed per second for the processor core or the second processor core;

the average instructions executed per second by a given thread;

the average cache accesses per second for the given thread; and

the average cache misses per second for the given thread.

15. The non-transitory computer-readable storage medium of claim 14, wherein characterizing the given thread involves using the measured metrics to determine whether the thread is one or more of the following:

cache-intensive;

cache-sensitive; and

cache-insensitive.

16. The non-transitory computer-readable storage medium of claim 15, wherein the method further comprises:

executing the second thread in a third processor core which is not associated with the cache;

executing a third thread in the second processor core;

measuring one or more metrics to characterize the second thread; and

measuring one or more metrics to characterize the third thread;

wherein predicting the performance impact involves using the characterization of the third thread and the characterization of the second thread in addition to the characterization of the first thread to determine whether migrating the second thread to the second processor core will improve performance for the multi-threaded processor.

17. The non-transitory computer-readable storage medium of claim 16, wherein predicting the performance impact involves predicting a degradation in the average instructions executed per second for one or more of the following:

the first thread;

the second thread; and

the third thread.

18. The non-transitory computer-readable storage medium of claim 17, where the method further comprises gathering data for thread characteristics and associated performance impacts by performing one or more of the following:

periodically migrating one or more threads between processor cores of the multi-threaded processor; and

opportunistically gathering data during normal multi-threaded execution in the multi-threaded processor.

19. The non-transitory computer-readable storage medium of claim 18, wherein the method further comprises:

using the gathered data as inputs to a forecasting system; and

using the forecasting system to predict the performance impact.

20. A multi-threaded processor that facilitates predictive thread scheduling, comprising:

a first processor core;

a second processor core;

a first cache associated with the first processor core and the second processor core;

a measurement mechanism that is configured to measure one or more metrics to characterize a first thread executing in the first processor core;

a prediction mechanism that is configured to use the characterization of the first thread and a characterization of a second thread to predict a performance impact associated with simultaneously executing the second thread in the second processor core; and

a scheduling mechanism that is configured to execute the second thread on the second processor core when the predicted performance impact indicates that executing the second thread on the second processor will improve performance for the multi-threaded processor.