Semiconductor Device and Manufacturing Method Thereof

• US 20110254008A1
• Filed: 06/27/2011
• Published: 10/20/2011
• Est. Priority Date: 07/22/1999
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Arai, Yasuyuki, Suzawa, Hideomi, Ono, Koji
• Granted Patent: US 8,624,248 B2
• Time in Patent Office: Days
• US Class Current: 257/59
• CPC Class Codes: G02F 1/13454 Drivers integrated on the active matrix substrate G02F1/136277 takes precedence
• CPC Class Codes: H01L 2029/7863 with an LDD consisting of more than one lightly doped zone or having a non-homogeneous dopant distribution, e.g. graded LDD
• CPC Class Codes: H01L 21/32136 using plasmas
• CPC Class Codes: H01L 27/1222 with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/1237 with a different composition, shape, layout or thickness of the gate insulator in different devices
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1277 using a crystallisation promoting species, e.g. local introduction of Ni catalyst
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78627 with a significant overlap between the lightly doped drain and the gate electrode, e.g. GOLDD
• CPC Class Codes: H01L 29/78645 with multiple gate

Abstract

By providing appropriate TFT structures arranged in various circuits of the semiconductor device in response to the functions required by the circuits, it is made possible to improve the operating performances and the reliability of a semiconductor device, reduce power consumption as well as realizing reduced manufacturing cost and increase in yield by lessening the number of processing steps. An LDD region of a TFT is formed to have a concentration gradient of an impurity element for controlling conductivity which becomes higher as the distance from a drain region decreases. In order to form such an LDD region having a concentration gradient of an impurity element, the present invention uses a method in which a gate electrode having a taper portion is provided to thereby dope an ionized impurity element for controlling conductivity accelerated in the electric field so that it penetrates through the gate electrode and a gate insulating film into a semiconductor layer.

Claims

1-36. -36. (canceled)

37. A semiconductor device comprising:

a first pixel over a substrate, and comprising;

a first TFT comprising;

a first portion of a first semiconductor layer comprising a first channel region, a pair of first LDD regions in contact with the first channel region, and first source and drain regions on the outside of the pair of first LDD regions;

a first gate insulating film over the first portion of the first semiconductor layer; and

a first gate electrode over the first gate insulating film, a capacitor comprising;

a first layer comprising a second portion of the first semiconductor layer;

a second layer over the first layer, and comprising a same layer as the first gate insulating film; and

a third layer over the second layer, and comprising a same layer as the first gate electrode,

an insulating film comprising silicon nitride, and over and in contact with the first gate electrode and the first gate insulating film,

wherein a third portion of the first semiconductor layer extends to a second pixel, and

wherein a thickness of the first gate insulating film over the first channel region is thicker than a thickness of the first gate insulating film over each of the first source and drain regions,

a driver circuit over the substrate, and comprising an n-channel TFT and a p-channel TFT,

wherein each of the n-channel TFT and the p-channel TFT comprises;

a second semiconductor layer comprising a second channel region, a pair of second LDD regions in contact with the second channel region, and second source and drain regions disposed on the outside of the pair of second LDD regions;

a second gate insulating film provided over the second semiconductor layer; and

a second gate electrode provided over the second gate insulating film, and

wherein a thickness of the second gate insulating film over the second channel region is thicker than a thickness of the second gate insulating film over each of the second source and drain regions.

38. A semiconductor device according to claim 37, wherein each of the first gate electrode, the second gate electrode and the third layer has a tapered portion.

39. A semiconductor device according to claim 38, wherein an angle of the tapered portion is between 5°

and 45°

.

40. A semiconductor device according to claim 37, wherein each of the first gate electrode and the second gate electrode comprises a heat resistant conductive material and a gate wiring that is electrically connected to the first gate electrode comprises a low resistivity conductive material.

41. A semiconductor device according to claim 40, wherein the heat resistant conductive material is selected from a group consisting of an element selected from tantalum, titanium, or tungsten.

42. A semiconductor device according to claim 37, wherein each of the first gate insulating film and the second gate insulating film comprises an insulating film containing silicon.

43. A semiconductor device according to claim 37, wherein a concentration of an impurity element in each of the pair of first LDD regions are set to become higher as the distance from the first channel region increases.

44. A semiconductor device according to claim 37, wherein the semiconductor device is applied to an electronic appliance selected from a group consisting of a personal computer, a video camera, a portable information terminal, a digital camera, a digital video disc player, an electronic game machine, and a projector.

45. A semiconductor device according to claim 37, wherein the first TFT has a multi gate structure.

46. A semiconductor device according to claim 43, wherein the second portion of the first semiconductor layer contains the impurity element.

47. A semiconductor device according to claim 37, wherein the first pixel and the second pixel are electrically connected to a same source wiring.

48. A semiconductor device according to claim 47, wherein a fourth portion of the first semiconductor layer is connected to the source wiring.

49. A semiconductor device comprising:

a first pixel over a substrate, and comprising;

a first TFT comprising;

a first portion of a first semiconductor layer comprising a first channel region, a pair of first LDD regions in contact with the first channel region, and first source and drain regions on the outside of the pair of first LDD regions;

a first gate insulating film over the first portion of the first semiconductor layer; and

a first gate electrode over the first gate insulating film, a capacitor comprising;

a first layer comprising a second portion of the first semiconductor layer;

a second layer over the first layer, and comprising a same layer as the first gate insulating film; and

a third layer over the second layer, and comprising a same layer as the first gate electrode,

an insulating film comprising silicon nitride, and over and in contact with the first gate electrode and the first gate insulating film,

wherein a third portion of the first semiconductor layer extends to a second pixel, and

wherein a thickness of the first gate insulating film over the first channel region is thicker than a thickness of the first gate insulating film over each of the first source and drain regions,

a driver circuit over the substrate, and comprising a second TFT,

wherein the second TFT comprises;

a second semiconductor layer comprising a second channel region, a pair of second LDD regions in contact with the second channel region, and second source and drain regions disposed on the outside of the pair of second LDD regions;

a second gate insulating film provided over the second semiconductor layer; and

a second gate electrode provided over the second gate insulating film, and

wherein a thickness of the second gate insulating film over the second channel region is thicker than a thickness of the second gate insulating film over each of the second source and drain regions.

50. A semiconductor device according to claim 49, wherein each of the first gate electrode, the second gate electrode and the third layer has a tapered portion.

51. A semiconductor device according to claim 50, wherein an angle of the tapered portion is between 5°

and 45°

.

52. A semiconductor device according to claim 49, wherein each of the first gate electrode and the second gate electrode comprises a heat resistant conductive material and a gate wiring that is electrically connected to the first gate electrode comprises a low resistivity conductive material.

53. A semiconductor device according to claim 52, wherein the heat resistant conductive material is selected from a group consisting of an element selected from tantalum, titanium, or tungsten.

54. A semiconductor device according to claim 49, wherein each of the first gate insulating film and the second gate insulating film comprises an insulating film containing silicon.

55. A semiconductor device according to claim 49, wherein a concentration of an impurity element in each of the pair of first LDD regions are set to become higher as the distance from the first channel region increases.

56. A semiconductor device according to claim 49, wherein the semiconductor device is applied to an electronic appliance selected from a group consisting of a personal computer, a video camera, a portable information terminal, a digital camera, a digital video disc player, an electronic game machine, and a projector.

57. A semiconductor device according to claim 49, wherein the first TFT has a multi gate structure.

58. A semiconductor device according to claim 55, wherein the second portion of the first semiconductor layer contains the impurity element.

59. A semiconductor device according to claim 49, wherein the first pixel and the second pixel are electrically connected to a same source wiring.

60. A semiconductor device according to claim 59, wherein a fourth portion of the first semiconductor layer is connected to the source wiring.

61. A semiconductor device comprising:

a first pixel over a substrate, and comprising;

a first TFT comprising;

a first portion of a first semiconductor layer comprising a first channel region, a pair of first LDD regions in contact with the first channel region, and first source and drain regions on the outside of the pair of first LDD regions;

a first gate insulating film over the first portion of the first semiconductor layer; and

a first gate electrode over the first gate insulating film, a capacitor comprising;

a first layer comprising a second portion of the first semiconductor layer;

a second layer over the first layer, and comprising a same layer as the first gate insulating film; and

a third layer over the second layer, and comprising a same layer as the first gate electrode,

an insulating film comprising silicon nitride, and over and in contact with the first gate electrode and the first gate insulating film; and

a first pixel electrode over the insulating film, and electrically connected to the first TFT,

wherein a third portion of the first semiconductor layer is overlapped with a second pixel electrode in a second pixel, and

wherein a thickness of the first gate insulating film over the first channel region is thicker than a thickness of the first gate insulating film over each of the first source and drain regions.

62. A semiconductor device according to claim 61, wherein each of the first gate electrode and the third layer has a tapered portion.

63. A semiconductor device according to claim 62, wherein an angle of the tapered portion is between 5°

and 45°

.

64. A semiconductor device according to claim 61, wherein the first gate electrode comprises a heat resistant conductive material and a gate wiring that is electrically connected to the first gate electrode comprises a low resistivity conductive material.

65. A semiconductor device according to claim 64, wherein the heat resistant conductive material is selected from a group consisting of an element selected from tantalum, titanium, or tungsten.

66. A semiconductor device according to claim 61, wherein the first gate insulating film comprises an insulating film containing silicon.

67. A semiconductor device according to claim 61, wherein a concentration of an impurity element in each of the pair of first LDD regions are set to become higher as the distance from the first channel region increases.

68. A semiconductor device according to claim 61, wherein the semiconductor device is applied to an electronic appliance selected from a group consisting of a personal computer, a video camera, a portable information terminal, a digital camera, a digital video disc player, an electronic game machine, and a projector.

69. A semiconductor device according to claim 61, wherein the first TFT has a multi gate structure.

70. A semiconductor device according to claim 67, wherein the second portion of the first semiconductor layer contains the impurity element.

71. A semiconductor device according to claim 61, wherein the first pixel and the second pixel are electrically connected to a same source wiring.

72. A semiconductor device according to claim 71, wherein a fourth portion of the first semiconductor layer is connected to the source wiring.