CONFIGURATION CONTEXT SWITCHER WITH A LATCH

• US 20110254586A1
• Filed: 04/18/2011
• Published: 10/20/2011
• Est. Priority Date: 09/06/2007
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Jason Redgrave, Martin Voogel, Trevis Chandler
• Inventors: Voogel, Martin, Redgrave, Jason, Chandler, Trevis
• Granted Patent: US 8,324,931 B2
• Time in Patent Office: Days
• US Class Current: 326/38
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H03K 19/0008 Arrangements for reducing power consumption
• CPC Class Codes: H03K 19/17732 Macroblocks
• CPC Class Codes: H03K 19/17748 Structural details of configuration resources
• CPC Class Codes: H03K 19/17752 for hot reconfiguration
• CPC Class Codes: H03K 19/17768 for security
• CPC Class Codes: H03K 3/0372 of the master-slave type

Abstract

Some embodiments provide an IC with configuration context switchers. The IC includes several configurable circuits, each of which configurably performs one of several operations at any given time, based on the configuration data set that it receives at that time. The IC includes several storage circuits for storing several configuration data sets for each of the configurable circuits. The IC also includes a context switching interconnect circuit for switchably connecting the configurable circuit to different sets of storage circuits to receive different sets of configuration data sets. The context switcher includes one or more stages for re-timing the data coming from the configuration storage elements. The stages can include interconnect circuitry or storage circuitry. Some embodiments build one of the stages in the configuration data storage elements. Some embodiments encode the configuration data bits and hence utilize a decoder in the context switcher to decode the encoded configuration data.

Claims

1-20. -20. (canceled)

21. An integrated circuit (“

IC”

) comprising;

a configurable circuit for configurably performing one of a plurality of operations based on configuration data;

a plurality of storage circuits for storing a plurality of configuration data sets for the configurable circuit;

an interconnect circuit for switchably connecting the configurable circuit to different sets of storage circuits to receive different configuration data sets, said interconnect circuit comprising a set of half-swing clock latches for temporarily storing configuration data sets, wherein the set of half-swing clock latches comprises a transistor that receives a half-swing clock signal with a voltage swing that is a fraction of a voltage difference between a supply voltage and a ground voltage for the interconnect circuit.

22. The IC of claim 21, wherein the half-swing clock signal does not fully turn on the transistor.

23. The IC of claim 21, wherein the transistor is a pass transistor of a transmission gate, wherein the half-swing clock signal is one of two half-swing clock signals received by the transmission gate.

24. The IC of claim 23, wherein the transmission gate comprises one NMOS transistor and one PMOS transistor.

25. The IC of claim 23, wherein the transmission gate allows current flow based on a voltage difference between the two half-swing clock signals.

26. The IC of claim 25, wherein the transmission gate allows current flow when both half-swing clock signals are at a mid-point voltage between the supply and ground voltages.

27. The IC of claim 25, wherein the transmission gate disallows current flow when one half-swing clock is at logic high and the other half-swing clock is at logic low.

28. The IC of claim 21, wherein the set of latches is further for (i) receiving different configuration data sets from different sets of storage circuits at different instances in time and (ii) temporarily storing each received particular configuration data set before providing the received particular configuration data set to the configurable circuit.

29. An electronic device comprising:

an integrated circuit (“

IC”

) comprising;

a configurable circuit for configurably performing one of a plurality of operations based on configuration data;

a plurality of storage circuits for storing a plurality of configuration data sets for the configurable circuit; and

an interconnect circuit for switchably connecting the configurable circuit to different sets of storage circuits to receive different configuration data sets, said interconnect circuit comprising a set of latches for temporarily storing configuration data sets, wherein the set of latches comprises a transistor that receives a half-swing clock signal with a voltage swing that is a fraction of a voltage difference between a supply voltage and a ground voltage for the interconnect circuit; and

a memory device for providing the configuration data to the IC.

30. The electronic device of claim 29, wherein the half-swing clock signal does not fully turn on the transistor.

31. The electronic device of claim 29, wherein the transistor is a pass transistor of a transmission gate, wherein the half-swing clock signal is one of two half-swing clock signals received by the transmission gate.

32. The IC of claim 31, wherein the transmission gate comprises one NMOS transistor and one PMOS transistor.

33. The electronic device of claim 31, wherein the transmission gate allows current flow based on a voltage difference between the two half-swing clock signals.

34. The electronic device of claim 33, wherein the transmission gate allows current flow when both half-swing clock signals are at a mid-point voltage between the supply and ground voltages.

35. The electronic device of claim 33, wherein the transmission gate disallows current flow when one half-swing clock is at logic high and the other half-swing clock is at logic low.

36. An integrated circuit (“

IC”

) comprising;

a configurable circuit for configurably performing one of a plurality of operations based on configuration data;

a plurality of storage circuits for storing a plurality of configuration data sets for the configurable circuit;

an interconnect circuit for switchably connecting the configurable circuit to different sets of storage circuits to receive different configuration data sets, said interconnect circuit comprising a transmission gate that allows current flow based on a half-swing signal with a voltage swing that is a fraction of a voltage difference a supply voltage and a ground voltages for the interconnect circuit.

37. The IC of claim 36, wherein the transmission gate comprises one NMOS transistor and one PMOS transistor.

38. The IC of claim 36, wherein the transmission gate allows current flow based on a voltage difference between said half-swing signal and another half-swing signal.

39. The IC of claim 38, wherein the transmission gate allows current flow when both half-swing clock signals are at a mid-point voltage between the supply and ground voltages.

40. The IC of claim 38, wherein the transmission gate disallows current flow when one half-swing signal is at the supply voltage and the other half-swing signal is at the ground voltage.

41. The IC of claim 36, wherein the interconnect circuit switchably connects the configurable circuit to different sets of storage circuits to receive different sets of configuration data sets in order to allow the configurable circuit to reconfigure while the IC is operating.