Pre-Distorting A Transmitted Signal For Offset Cancellation

• US 20110255581A1
• Filed: 06/22/2011
• Published: 10/20/2011
• Est. Priority Date: 09/24/2007
• Status: Active Grant

• Current Assignee: Panasonic Electric Works Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Panasonic Electric Works Company Limited (Panasonic Holdings Corporation)
• Inventors: Sumesaglam, Taner, Martin, Aaron
• Granted Patent: US 8,213,887 B2
• Time in Patent Office: Days
• US Class Current: 375/222
• CPC Class Codes: H04L 25/028 Arrangements specific to the transmitter end

Abstract

In one embodiment, the present invention includes a pre-driver to receive data of a first clock phase and to pre-drive the data, a driver coupled to the pre-driver to drive the data onto a link operable to be coupled to a receiver, and an offset driver to drive an offset value associated with the first clock phase onto the link with the data. Other embodiments are described and claimed.

Claims

1. A method comprising:

generating an offset for a first clock phase of a multi-phase clock during a training interval in an offset driver, wherein the offset is varied during at least some iterations of the first clock phase, wherein a data bit of an n-bit data is to be selected at the first clock phase;

transmitting the offset from a first device including the offset driver to a second device along a link;

receiving an indication in the first device that a signal corresponding to the offset has been detected in the second device with a predetermined density of a first logic level; and

storing an offset code in an offset register of the first device corresponding to the offset when the indication is received, the offset to correct an offset present in an interleaved receiver of the second device corresponding to the first clock phase.

2. The method of claim 1, further comprising shorting a pre-driver coupled to a driver of a signal path during the training interval.

3. The method of claim 2, further comprising generating and transmitting the offset, receiving the indication and storing the offset code for each of a plurality of clock phases of the multi-phase clock, wherein at each of the plurality of clock phases a different data bit of the n-bit data is to be selected.

4. The method of claim 2, further comprising generating a data value in the signal path, combining the data value with an offset value generated by the stored offset code, and providing the combined data value and offset value from the first device to the second device during normal operation.

5. The method of claim 1, further comprising predistorting a data value with the stored offset code to condition the data value for distortion in the link.

6. The method of claim 5, further comprising recovering the data value in the second device without performing offset correction in the second device.

7. The method of claim 6, wherein the first device includes a memory controller, and the second device includes a memory coupled to the memory controller.

8. An apparatus comprising:

a pre-driver to receive data based on a first clock phase of a multi-phase clock and to pre-drive the data;

a driver coupled to the pre-driver to drive the data onto a link operable to be coupled to a receiver; and

an offset driver to drive an offset value associated with the first clock phase onto the link with the data, wherein the offset value is to correct an offset present in an interleaved receiver of the receiver corresponding to the first clock phase.

9. The apparatus of claim 8, further comprising selection logic to receive data of a plurality of clock phases and to output the data of the first clock phase to the pre-driver, wherein the selection logic is controlled by the plurality of clock phases.

10. The apparatus of claim 9, further comprising:

offset logic coupled to the offset driver to provide an offset correction code to the offset driver, wherein the offset value is generated in the offset driver based on the offset correction code;

second selection logic coupled to the offset logic to select one of a plurality of offset correction codes to output to the offset driver based on the first clock phase; and

a digital-to-analog converter to receive the offset correction code from the second selection logic and to output the offset value to the offset driver.

11. The apparatus of claim 10, wherein the offset logic is operable to provide a plurality of varying values for the first clock phase during a training interval to generate the offset correction code.

12. The apparatus of claim 11, wherein the offset logic is operable to select one of the plurality of varying values to be the offset correction code when the receiver has detected the offset value with a predetermined density of a first logic level and to store the offset correction code in a storage.

13. The apparatus of claim 9, further comprising:

offset logic coupled to the offset driver to provide a plurality of offset correction codes, wherein the offset value is generated in the offset driver based on one of the offset correction codes;

a plurality of digital-to-analog converters to each receive one of the offset correction codes and to output an analog correction code; and

second selection logic coupled to the digital-to-analog converters to select one of the analog correction codes to output to the offset driver based on a given one of the plurality of clock phases.

14. The apparatus of claim 13, wherein the offset logic is operable to provide a plurality of varying values during a training interval to generate each of the plurality of offset correction codes and to select one of the plurality of varying values to be the offset correction code when the receiver has detected the offset value with a predetermined density of a first logic level and to store the offset correction code in a storage.

15. A system comprising:

a first device including;

a pre-driver to receive a datum of a multi-bit data based on a corresponding clock phase of a multi-phase clock and to pre-drive the datum, a driver coupled to the pre-driver to drive the datum onto a link, and an offset driver to drive an offset value associated with the corresponding clock phase onto the link with the datum; and

a second device coupled to the first device via the link, the second device including;

a plurality of interleaved receivers each to capture the datum and the offset value for one of the corresponding clock phases of the multi-phase clock, wherein the offset value is to correct an offset present in the interleaved receiver of the corresponding clock phase.

16. The system of claim 15, wherein the first device is to generate an offset for a first clock phase of the multi-phase clock during a training interval in the offset driver, the offset varied during at least some iterations of the first clock phase, transmit the offset from the first device along the link, receive an indication in the first device that a signal corresponding to the offset has been detected in the second device with a predetermined density of a first logic level, and store an offset code in an offset register of the first device corresponding to the offset when the indication is received.

17. The system of claim 16, wherein the first device is to short a pre-driver coupled to a driver of a signal path during the training interval.