HIGH POWER FET SWITCH

• US 20110260774A1
• Filed: 04/27/2011
• Published: 10/27/2011
• Est. Priority Date: 04/27/2010
• Status: Active Grant

• Current Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Original Assignee: RF Micro Devices Incorporated (Qorvo, Inc.)
• Inventors: Iversen, Christian Rye, Granger-Jones, Marcus
• Granted Patent: US 10,056,895 B2
• Time in Patent Office: Days
• US Class Current: 327/427
• CPC Class Codes: H03K 17/102 in field-effect transistor switches

Abstract

Described are embodiments of stacked field effect transistor (FET) switch having a plurality of FET devices coupled in series to form an FET device stack. To prevent the FET device stack from being turned on during large signal conditions, a first decoupling path and a second decoupling path are provided for the first FET device and the last FET device in the FET device stack. Both decoupling paths are configured to pass a time-variant input signal during the open state. The first decoupling path may be coupled from the drain contact of the first FET device to the gate contact or the source contact. The second decoupling path may be coupled from the source contact of the last FET device to the gate contact or drain contact. The time-variant input signal bypasses the FET device stack through the first and second decoupling paths during the open state.

Claims

1. A stacked field effect transistor (FET) switch for a time-variant input signal, the FET switch comprising:

a FET device stack operable in an open state and in a closed state, the FET device stack comprising a plurality of FET devices coupled in series to form the FET device stack;

the plurality of FET devices including at least a first FET device, one or more middle FET devices, and a last FET device, each of the plurality of FET devices having a gate contact, a drain contact, and a source contact, wherein the drain contact of the first FET device is at a first end of the FET device stack, and the source contact of the last FET device is at a second end of the FET device stack, and wherein the one or more middle FET devices are coupled in the FET device stack between the first FET device and the last FET device;

a first decoupling path configured to pass the time-variant input signal during the open state of the FET device stack, the first decoupling path being connected to the FET device stack such that the time-variant input signal bypasses the FET device stack from the drain contact of the first FET device to either the gate contact of the first FET device or the source contact of the first FET device during the open state; and

a second decoupling path configured to pass the time-variant input signal during the open state of the FET device stack, the second decoupling path being connected to the FET device stack such that the time-variant input signal bypasses the FET device stack from either the drain contact of the last FET device or the gate contact of the last FET device to the source contact of the last FET device during the open state.

2. The stacked FET switch of claim 1, wherein the first decoupling path further comprises a capacitor.

3. The stacked FET switch of claim 1, wherein the second decoupling path further comprises a capacitor.

4. The stacked FET switch of claim 1, wherein:

the first decoupling path further comprises a first capacitor; and

the second decoupling path further comprises a second capacitor.

5. The stacked FET switch of claim 1, wherein:

the first decoupling path is connected to the FET device stack such that the time-variant input signal bypasses the FET device stack from the drain contact of the first FET device to the gate contact of the first FET device during the open state; and

the first decoupling path being connected between the drain contact of the first FET device to the gate contact of the first FET device.

6. The stacked FET switch of claim 1, wherein the second decoupling path is connected between the either the drain contact of the last FET device or the gate contact of the last FET device and the source contact of the last FET device.

7. The stacked FET switch of claim 1, wherein the second decoupling path is connected between the either the drain contact of the last FET device or the gate contact of the last FET device and a ground node.

8. The stacked FET switch of claim 1, further comprising:

wherein the second decoupling path being connected to the FET device stack such that the time-variant input signal bypasses the FET device stack from the gate contact of the last FET device to the source contact of the last FET device during the open state;

a third decoupling path configured to pass the time-variant input signal during the open state of the FET device stack, the third decoupling path being connected to the FET device stack such that the time-variant input signal bypasses the FET device stack from the drain contact of the last FET device to the source contact of the last FET device during the open state.

9. The stacked FET switch of claim 1, further comprising:

an input terminal for receiving the time-variant input signal;

an output terminal; and

the FET device stack being connected between the input terminal and the output terminal.

10. The stacked FET switch of claim 9, wherein the first end of the FET device stack is directly connected to the input terminal.

11. The stacked FET switch of claim 9, wherein the second end of the FET device stack is directly connected to the output terminal.

12. The stacked FET switch of claim 9, wherein the first decoupling path is connected directly to the input terminal and the either the gate contact of the first FET device or the source contact of the first FET device.

13. The stacked FET switch of claim 9, wherein the second decoupling path is connected between the either the drain contact of the last FET device or the gate contact of the first FET device and the output terminal.

14. The stacked FET switch of claim 9, further comprising:

each of the plurality of FET devices having a body contact;

the body contact of the first FET device being directly connected to the input terminal; and

the body contact of the last FET device being directly connected to the output terminal.

15. The stacked FET switch of claim 14, further comprising:

a resistive circuit coupled to each of the body contacts of the one or more middle FET devices, the resistive circuit providing a high resistance at each of the body contacts of the one or more middle FET devices so as to render parasitic capacitances between the body contact and the drain and source contacts of each of the one or more middle FET devices negligible.

16. The stacked FET switch of claim 1, further comprising:

a resistive circuit coupled to each of the gate contacts of the plurality of FET devices, the resistive circuit providing a high resistance at each of the gate contacts of the plurality of FET devices so as to render parasitic capacitances between the gate contact and the drain and source contacts of each of the plurality of FET devices negligible.

17. The stacked FET switch of claim 16, further comprising a control circuit operably associated with the FET device stack, the control circuit being configured to:

bias the gate contacts of each of the plurality of FET devices at a first voltage such that the FET device stack operates in the closed state;

the first voltage being positive relative to a reference voltage;

bias the gate contact of each of the plurality of FET devices at a second voltage and bias the drain contacts and source contacts of each of the one or more middle FET devices at the first voltage, such that the FET device stack operates in the open state; and

the second voltage being less than the first voltage and non-negative relative to the reference voltage.

18. The stacked FET switch of claim 17, wherein the control circuit is further configured to bias the drain contacts and source contacts of each of the middle FET devices at the second voltage during the closed state.

19. The stacked FET switch of claim 17, wherein the first decoupling path and the second decoupling path are configured to block DC bias voltages.

20. The stacked FET switch of claim 17, wherein:

the first decoupling path further comprises a bypass transistor; and

the control circuit being configured to turn on the bypass transistor when the FET device stack is in the open state and turn off the bypass transistor when the FET device stack is in the closed state.

21. The stacked FET switch of claim 17, wherein:

the second decoupling path further comprises a bypass transistor; and

the control circuit being configured to turn on the bypass transistor when the FET device stack is in the open state and turn off the first bypass transistor when the FET device stack is in the closed state.

22. The stacked FET switch of claim 17, wherein the drain contacts and source contacts of each of the plurality of FET devices are coupled so that biasing the drain contact and the source contact of each of the one or more middle FET devices biases the source contact of the first FET device.

23. The stacked FET switch of claim 17, wherein the drain contacts and source contacts of each of the plurality of FET devices are operably associated with one another such that biasing the drain contact and the source contact of each of the one or more middle FET devices biases the drain contact of the last FET device.

24. A stacked field effect transistor (FET) switch for a time-variant input signal, the FET switch comprising:

a FET device stack operable in an open state and in a closed state, the FET device stack comprising a plurality of FET devices coupled in series to form the FET device stack, the FET device stack having a first end and a second end;

the plurality of FET devices each having a gate contact, a drain contact, and a source contact;

a first decoupling path configured to pass the time-variant input signal during the open state of the FET device stack, the first decoupling path being connected between the first end of the FET device stack and either the gate contact or the source contact of one of the plurality of FET devices; and

a second decoupling path configured to pass the time-variant input signal during the open state of the FET device stack, the second decoupling path being connected between the second end of the FET device stack and either the gate contact or the drain contact of another one of the plurality of FET devices.