NONVOLATILE MEMORY DEVICE HAVING OPERATION MODE CHANGE FUNCTION AND OPERATION MODE CHANGE METHOD

• US 20110264845A1
• Filed: 02/28/2011
• Published: 10/27/2011
• Est. Priority Date: 04/27/2010
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: CHOI, Chang-Eun
• Application Number:
  US13/036,247
• Publication Number:
  US 20110264845A1
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/102 External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
• CPC Class Codes: G11C 16/32 Timing circuits

Abstract

A nonvolatile semiconductor memory device changes an operation mode according to method type of operation to be performed. The semiconductor memory device includes a cache register for supporting a cache operation mode. The cache register and the memory cell array operate in the cache operation mode according to a first operation command. The memory cell array operates in an operation mode different from the cache operation mode according to a second operation command.

Claims

1. A method of driving a nonvolatile semiconductor memory device including a cache register for supporting a cache operation mode, the method comprising:

driving the nonvolatile semiconductor memory device in the cache operation mode according to a first operation command; and

driving the nonvolatile semiconductor memory device in an operation mode different from the cache operation mode according to a second operation command.

2. The method of claim 1, wherein the first operation command is a writing operation command.

3. The method of claim 1, wherein the second operation command is a moving operation command when the first operation command is a writing operation command.

4. The method of claim 1, wherein the operation mode different from the cache operation mode is a Double Data Rate (DDR) operation mode.

5. The method of claim 1, wherein an operation clock frequency, which is used in the nonvolatile semiconductor memory device under the second operation command, differs from an operation clock frequency which is used in the nonvolatile semiconductor memory device under the first operation command.

6. The method of claim 1, wherein an operation clock frequency, which is used in the nonvolatile semiconductor memory device under the second operation command, is higher than an operation clock frequency which is used in the nonvolatile semiconductor memory device under the first operation command.

7. The method of claim 1, wherein the nonvolatile semiconductor memory device is a NAND flash memory device.

8. The method of claim 1, wherein a memory device configuring the cache register is configured in a type different from a type of a memory cell which configures a memory cell array of the nonvolatile semiconductor memory device.

9. A nonvolatile semiconductor memory device comprising:

a cache register supporting a cache operation mode;

a memory cell array comprising a plurality of memory blocks which comprise a plurality of memory cells nonvolatilely storing data; and

a control driver to drive the cache register and the memory cell array in the cache operation mode according to a first operation command, and to drive the memory cell array in an operation mode different from the cache operation mode according to a second operation command.

10. The nonvolatile semiconductor memory device of claim 9, wherein the first operation command is a writing operation command which indicates loading of data into the cache register and writing of the loaded data in the memory cell array.

11. The nonvolatile semiconductor memory device of claim 9, wherein when the first operation command is a writing operation command, the second operation command is a moving operation command which indicates reading of data from a memory cell and writing of the read data into another memory cell.

12. The nonvolatile semiconductor memory device of claim 9, wherein the operation mode different from the cache operation mode is a Double Data Rate (DDR) operation mode.

13. The nonvolatile semiconductor memory device of claim 9, wherein an operation clock frequency, which is used under the second operation command, differs from an operation clock frequency which is used under the first operation command.

14. The nonvolatile semiconductor memory device of claim 9, wherein an operation clock frequency, which is used in the nonvolatile semiconductor memory device under the second operation command, is higher than an operation clock frequency which is used in the nonvolatile semiconductor memory device under the first operation command.

15. The nonvolatile semiconductor memory device of claim 14, wherein a memory device configuring the cache register comprises a latch type of volatile memory cell.

16. A data processing system comprising:

a nonvolatile semiconductor memory device comprising a cache register supporting a cache operation mode, and a memory cell array comprising a plurality of memory blocks which comprise a plurality of memory cells nonvolatilely storing data; and

a memory controller to control the nonvolatile semiconductor memory device to operate in the cache operation mode according to a first operation command, and to operate in an operation mode different from the cache operation mode according to a second operation command.

17. The data processing system of claim 16, wherein an operation clock frequency, which is used in the nonvolatile semiconductor memory device under the second operation command, is higher than an operation clock frequency which is used in the nonvolatile semiconductor memory device under the first operation command.

18. The data processing system of claim 16, wherein the nonvolatile semiconductor memory device is a OneNAND flash memory device.

19. The data processing system of claim 16, wherein when the first operation command is a writing operation command which indicates loading of data into the cache register and writing of the loaded data in the memory cell array, the second operation command is a moving operation command which indicates reading of data from a memory cell and writing of the read data into another memory cell.

20. The data processing system of claim 19, wherein the data processing system is comprised in a mobile device.

21. A method of controlling a memory device, the method comprising:

receiving a command to perform an operation of the memory device;

determining whether the command corresponds to a first type of operation; and

when the command corresponds to the first type of operation, performing the operation in a cache mode, and when the command does not correspond to the first type of operation, performing the operation in a non-cache mode.

22. The method of claim 21, wherein performing the operation in the cache mode includes selecting a first clock signal to perform the operation, and

performing the operation in the non-cache mode includes selecting a second clock signal different from the first clock signal to perform the operation.

23. The method of claim 22, wherein the second clock signal has a frequency higher than the first clock signal.

24. The method of claim 21, wherein the first operation is a write operation to write data into a memory block of the memory device.

25. The method of claim 21, further comprising:

after receiving the command, determining whether a hybrid mode is set; and

when it is determined that the hybrid mode is set, determining whether the command corresponds to the first type of operation, and when it is determined that the hybrid mode is not set, setting the mode to a predetermined one of the cache mode and the non-cache mode to perform the operation without determining whether the command corresponds to the first type of operation.

26. A nonvolatile memory device, comprising:

a memory cell array to store data; and

a control unit to receive a command to perform an operation, to execute the operation in a cache mode when the operation is a first type of operation, and to execute the operation in a non-cache mode when the operation is not the first type of operation.

27. The non-volatile memory device of claim 26, further comprising:

a clock generator to generate a first clock signal having a first frequency and a second clock signal having a second frequency different from the first clock signal; and

a clock selection circuit to select and output the first clock signal to execute the operation when the operation is performed in the cache mode, and to select and output the second clock signal to execute the operation when the operation is performed in the non-cache mode.

28. The non-volatile memory device of claim 27, wherein the second clock signal has a frequency higher than the first clock signal.

29. The non-volatile memory device of claim 26, further comprising a cache register,

wherein performing the operation in the cache mode includes storing data in the cache register and transmitting the data from the cache register to the memory cell array to store the data in the memory cell array.

30. A memory controller, comprising:

a control circuit to receive a command to perform an operation corresponding to a nonvolatile memory controlled by the memory controller, to determine whether the operation corresponds to a predetermined operation type, and to output a first mode determination signal to perform the operation in a cache mode when the operation corresponds to the predetermined type and to output a second mode determination signal to perform the operation in a non-cache mode when the operation does not correspond to the predetermined type.

31. The memory controller of claim 30, further comprising:

a clock generator to generate a first clock signal having a first frequency and a second clock signal having a second frequency different from the first clock signal; and

a clock selection circuit to select and output the first clock signal to execute the operation when the operation corresponds to the predetermined operation type, and to select and output the second clock signal to execute the operation when the operation does not correspond to the predetermine operation type.

32. The memory controller of claim 30, further comprising:

a register to store data indicating whether a hybrid mode is selected,

wherein the control circuit detects whether the hybrid mode is selected, and

when the hybrid mode is selected, the control circuit determines whether the operation corresponds to the predetermined type of operation, and when the hybrid mode is not selected, the control circuit outputs a predetermined one of the first and second mode determination signals regardless of whether the operation corresponds to the predetermined type of operation.

33. An electronic device, comprising:

a nonvolatile memory device to store data; and

a memory controller to receive a command to control the nonvolatile memory to perform an operation, to determine whether the operation corresponds to a predetermined operation type, and to output a first mode determination signal to control the nonvolatile memory device to perform the operation in a cache mode when the operation corresponds to the predetermined type and to output a second mode determination signal to control the nonvolatile memory device to perform the operation in a non-cache mode when the operation does not correspond to the predetermined type.

34. A memory device, comprising:

a memory cell array; and

a controller to control the memory cell array to perform a first operation using a first clock having a first speed in a first mode, and to perform a second operation different from the first operation using a second clock having a second speed different from the first speed in a second mode different from the first mode.