Addressing, Command Protocol, and Electrical Interface for Non-Volatile Memories Utilized in Recording Usage Counts

• US 20110264850A1
• Filed: 06/30/2011
• Published: 10/27/2011
• Est. Priority Date: 06/16/2005
• Status: Active Grant

• Current Assignee: Lexmark International Incorporated (Ninestar Corporation)
• Original Assignee: Bryan Scott Willett, James Ronald Booth
• Inventors: Booth, James Ronald, Willett, Bryan Scott
• Granted Patent: US 8,966,193 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G11C 16/32 Timing circuits
• CPC Class Codes: G11C 7/109 Control signal input circuits

Abstract

Electrical interfaces, addressing schemes, and command protocols allow for communications with memory modules in computing devices such as imaging and printing devices. Memory modules may be assigned an address through a set of discrete voltages. One, multiple, or all of the memory modules may be addressed with a single command, which may be an increment counter command, a write command, a punch out bit field, or a cryptographic command. The commands may be transmitted using a broadcast scheme or a split transaction scheme. The status of the memory modules may be determined by sampling a single signal that may be at a low, high, or intermediate voltage level.

Claims

1-20. -20. (canceled)

21. A method of updating a memory module, comprising:

receiving, at a memory module, a command indicative of usage of toner or ink in a consumable item for an imaging device for instructing the memory module to punch out at least one specified bit within the memory module indicative of the usage of toner or ink; and

processing the command at the memory module.

22. The method of claim 21, wherein the processing of the command comprises changing the at least one specified bit from an erased state to a programmed state.

23. The method of claim 21, wherein the at least one specified bit comprises at plurality of bits.

24. The method of claim 23, wherein the plurality of bits comprises at least eight bits.

25. The method of claim 21, wherein the command is operable to instructs the memory module to increment a counter therein.

26. The method of claim 25, wherein the processing comprises incrementing the counter by an amount specified in the command.

27. The method of claim 25, wherein the processing comprises at least one of changing the at least one specified bit from an erased state to a programmed state and incrementing the counter.

28. The method of claim 27, wherein incrementing the counter comprises incrementing the counter by an amount specified in the command.

29. The method of claim 21, wherein the processing comprises:

initially pulling a first interface signal of the memory module to a first voltage level corresponding to a binary zero state; and

upon encountering an error condition while processing the command, placing the first interface signal at a second intermediate voltage greater than the first voltage level and less than a third voltage level corresponding to a binary one state.

30. A memory module, comprising:

a plurality of memory bits, wherein the memory module receives at least one command indicative of usage of toner or ink in a consumable item for an imaging device and instructing the memory module to punch out at least one specified bit within the memory module indicative of the usage of toner or ink, and processes the at least one command.

31. The memory module of claim 30, wherein the memory module processes the at least one command by changing the at least one specified bit from an erased state to a programmed state.

32. The memory module of claim 30, wherein the at least one specified bit comprises at plurality of bits.

33. The memory module of claim 30, wherein the memory module includes a counter and the at least one command instructs the memory module to increment a counter therein.

34. The memory module of claim 33, wherein the memory module processes the at least one command by performing at least one of changing the at least one specified bit from an erased state to a programmed state and incrementing the counter.

35. The memory module of claim 34, wherein the memory module processes the at least one command by incrementing the counter by an amount specified in the at least one command.

36. The memory module of claim 30, wherein the memory module includes a first interface signal for communicating with a processing device, the memory module processes the at least one command by:

initially pulling the first interface signal of the memory module to a first voltage level corresponding to a binary zero state; and

upon encountering an error condition while processing the at least one command, placing the first interface signal at a second intermediate voltage greater than the first voltage level and less than a third voltage level corresponding to a binary one state.

37. A memory module, comprising:

a plurality of memory cells; and

a plurality of signals for communicating with a processing device, the memory module configured such that following reception of a command, a first signal of the plurality of signals is initially pulled to a first voltage level corresponding to a binary zero state and upon encountering an error condition while processing the command, the first signal is placed at a second intermediate voltage greater than the first voltage level and less than a third voltage level corresponding to a binary one state.

38. The memory module of claim 37, wherein the command is indicative of usage of toner or ink in a consumable item for an imaging device and instructs the memory module to punch out at least one specified cells within the memory module indicative of the usage of toner or ink, following reception of the command, the memory module processes the at least one command.

39. The memory module of claim 38, wherein the memory module processes the command by changing the at least one specified cell from an erased state to a programmed state.