TCE COMPENSATION FOR PACKAGE SUBSTRATES FOR REDUCED DIE WARPAGE ASSEMBLY

• US 20110266693A1
• Filed: 04/29/2010
• Published: 11/03/2011
• Est. Priority Date: 04/29/2010
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Simmons-Matthews, Margaret Rose
• Granted Patent: US 8,298,863 B2
• Time in Patent Office: Days
• US Class Current: 257/774
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/68331 of passive members, e.g. die mounting substrate
• CPC Class Codes: H01L 2221/68368 used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/16148 the bump connector connecting to a bonding area protruding from the surface
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/17181 On opposite sides of the body
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/81801 : Soldering or alloying
• CPC Class Codes: H01L 2224/81895 : between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49894 : Materials of the insulating layers or coatings
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01058 : Cerium [Ce]
• CPC Class Codes: H01L 2924/0106 : Neodymium [Nd]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

A method for assembling die packages includes attaching contacts on a first side of a plurality of first die to substrate pads on a top surface of a composite carrier. The composite carrier includes a package substrate including at least one embedded metal layer having its bottom surface secured to a semiconductor wafer. The composite carrier minimizes effects of the CTE mismatch between the die and the package substrate during assembly reduces warpage of the die. After the attaching, the semiconductor wafer is removed from the package substrate. Electrically conductive connectors are attached to the bottom surface of the package substrate, and the package substrate is sawed to form a plurality of singulated die packages.

Claims

1. A method for assembling die packages, comprising:

attaching contacts on a first side of a plurality of first die to substrate pads on a top surface of a composite carrier, wherein said composite carrier comprises a package substrate including at least one embedded metal layer having its bottom surface secured to a semiconductor wafer;

after said attaching, removing said semiconductor wafer from said package substrate;

attaching a plurality of electrically conductive connectors to said bottom surface of said package substrate, and

sawing said package substrate to form a plurality of singulated die packages.

2. The method of claim 1, wherein said semiconductor wafer comprises a silicon wafer and said package substrate comprises an organic substrate.

3. The method of claim 1, wherein said plurality of first die are disposed on a wafer.

4. The method of claim 1, wherein said plurality of first die comprise singulated die.

5. The method of claim 1, wherein said plurality of electrically conductive connectors comprise a ball grid array (BGA).

6. The method of claim 1, wherein said plurality of first die comprises through substrate via (TSV) die that include TSVs, wherein said contacts include contacts to said TSVs.

7. The method of claim 6, further comprising:

thinning a second side of said plurality of TSV die to expose said TSVs to provide exposed TSV areas, and

attaching a plurality of singulated second die to TSV contacts coupled to said exposed areas to form a plurality of die stacks on said package substrate.

8. A method for assembling stacked die packages, comprising:

attaching contacts on a first side of a plurality of first die to substrate pads on a top surface of a composite carrier, wherein said composite carrier comprises a package substrate including at least one embedded metal layer having its bottom surface secured to a semiconductor wafer;

attaching a plurality of singulated second die to said first die to form a plurality of die stacks on said package substrate;

removing said semiconductor wafer from said package substrate;

attaching a plurality of electrically conductive connectors to said bottom surface of said package substrate, and

sawing said package substrate to form a plurality of singulated stacked die packages.

9. The method of claim 8, wherein said semiconductor wafer comprises a silicon wafer and said package substrate comprises an organic substrate.

10. The method of claim 8, wherein said plurality of first die comprises through substrate via (TSV) die that include TSVs, wherein said contacts include contacts to said TSVs.

11. The method of claim 10, further comprising:

thinning a second side of said plurality of TSV die to expose said TSVs to provide exposed TSV areas, and

attaching a plurality of singulated second die to said TSV contacts coupled to said exposed areas to form a plurality of die stacks on said package substrate.

12. The method of claim 8, wherein said plurality of first die are disposed on a wafer.

13. The method of claim 8, wherein said plurality of first die comprise singulated die.

14. A method for assembling stacked die packages, comprising:

attaching a topside of a plurality of singulated through substrate via (TSV) die having embedded TSVs including topside pads coupled to said TSVs to substrate pads on a top surface of a composite carrier, said composite carrier comprising an organic substrate including at least one embedded metal layer having its bottom surface secured to a silicon wafer;

thinning a bottomside of said plurality of singulated TSV die to provide exposed TSV areas;

forming bottomside TSV contacts on said exposed TSV areas;

attaching a plurality of singulated second die to said bottomside TSV contacts to form a plurality of die stacks on said organic substrate;

removing said silicon wafer from said organic substrate;

attaching a plurality of electrically conductive connectors to said bottom surface of said organic substrate, and

sawing through said organic substrate to form a plurality of singulated stacked die packages.

15. The method of claim 14, wherein said plurality of TSV die are disposed on a TSV wafer.

16. The method of claim 14, wherein said plurality of TSV die comprise singulated TSV die.

17. An electronic assembly, comprising:

a composite carrier comprising an organic package substrate including at least one embedded metal layer having its bottom surface secured to a semiconductor wafer, and

a plurality of first die having a thickness of 20 to 100 μ

m having their topside contacts attached to topside substrate pads on a top surface of said package substrate.

18. The electronic assembly of claim 17, wherein said plurality of first die comprise through substrate via (TSV) die that include TSVs that have said topside contacts coupled to said TSVs attached to topside substrate pads of said package substrate.

19. The electronic assembly of claim 17, further comprising a plurality of singulated second die attached to bottomside contacts that are coupled to said TSVs.

20. The electronic assembly of claim 17, wherein said semiconductor wafer comprises a silicon wafer.

21. The electronic assembly of claim 17, wherein said plurality of first die are disposed on a first wafer.