APPARATUS AND METHOD FOR WAFER LEVEL CLASSIFICATION OF LIGHT EMITTING DEVICE

• US 20110267087A1
• Filed: 04/28/2010
• Published: 11/03/2011
• Est. Priority Date: 04/28/2010
• Status: Active Grant

• Current Assignee: Epistar Corporation
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Huang, Hsin-Chieh
• Granted Patent: US 8,476,918 B2
• Time in Patent Office: Days
• US Class Current: 324/754.23
• CPC Class Codes: G01R 31/2635 Testing light-emitting diodes, laser diodes or photodiodes
• CPC Class Codes: G01R 31/2889 Interfaces, e.g. between probe and tester G01R31/31905 and G01R1/07364 take precedence
• CPC Class Codes: G01R 31/311 of integrated circuits G01R31/31728 takes precedence
• CPC Class Codes: G09G 3/006 Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays testing individual LED's G01R31/2635; testing lamps G01R31/44; testing of optical features of LCD displays G02F1/1309

Abstract

The present disclosure provides a semiconductor test system. The semiconductor test system includes a wafer stage to hold a wafer having a plurality of light emitting devices (LEDs); a probe test card operable to test each test field of the wafer; and a light detector integrated with the probe test card to collect light from a LED of the wafer.

Claims

1. A semiconductor test system, comprising:

a wafer stage to hold a wafer having a plurality of light emitting devices (LEDs);

a probe test card operable to test each test field of the wafer; and

a light detector integrated with the probe test card to collect light from a LED of the wafer.

2. The semiconductor test system of claim 1, further comprising a shield structure designed and configured to block environmental light from reaching the light detector.

3. The semiconductor test system of claim 1, wherein the shield structure is configured around the wafer stage to shield the light detector and the wafer from the environmental light.

4. The semiconductor test system of claim 1, wherein the light detector is integrated with the probe test card and is configured to move relative to the probe test card.

5. The semiconductor test system of claim 4, wherein the probe test card further includes a track configured such that the light detector is operable to move along the track.

6. The semiconductor test system of claim 5, wherein the track is designed to a pattern such that the light detector is operable to move close to any location of the probe test card within a predefined distance.

7. The semiconductor test system of claim 5, wherein the track is designed such that the light detector is operable to move to a location for test any die in a test field of the wafer.

8. The semiconductor test system of claim 1, wherein the probe test card is operable to move to any test field of the wafer on the wafer stage.

9. The semiconductor test system of claim 1, further comprising a control module including:

a probe sub-module designed to control the probe test card in a test operation; and

a light detector sub-module designed to control the light detector in the test operation.

10. The semiconductor test system of claim 1, further comprising a plurality of light detectors configured on the probe test card in an array and capable of parallel testing a plurality of dies in a test field of the wafer.

11. A method, comprising:

providing a semiconductor test system for testing a wafer, wherein the semiconductor test system includes;

a wafer stage to hold a wafer;

a probe test card operable to test each test field of the wafer; and

a light detector integrated with the probe test card to collect light from the wafer;

providing a wafer having a plurality of light emitting devices (LEDs) to the wafer stage; and

testing a die of a test field on the wafer using the light detector for optical and electrical performance of the die.

12. The method of claim 11, further comprising:

repeating the testing to a next die of the test field by moving the light detector near a next die; and

repeating the test to other test fields of the wafer.

13. The method of claim 11, wherein the testing a die of a test field includes:

positioning the probe card to the test field of the wafer; and

positioning the light detector near the die.

14. The method of claim 11, wherein the testing a die further includes:

collecting light from a light emitting device (LED) of the die; and

normalizing light intensity by a formula as I=K×

Cosine (A)×

Ic/d², wherein Ic is the light collected from the LED, A is an angle of the light and d is a distance from the LED to the light detector.

15. The method of claim 11, further comprising:

sawing the die from the wafer; and

packaging the die if the die passes the testing.

16. The method of claim 11, further comprising classifying the die into a bin according to the optical and electrical performance of the die.

17. The method of claim 11, further comprising:

testing a plurality of dies of the wafer using the light detector for optical and electrical parameters;

classifying the plurality of dies into different bins according to respective values of the optical and electrical parameters; and

packaging each of the plurality of dies according to respective bin.

18. The method of claim 17, wherein the packaging each of plurality of dies includes using a package technology selected from the group consisting of ceramic package, plastic package, and plastic package plus heat sink.

19. The method of claim 17, further comprising integrating each of the plurality of dies into a respective application unit according to respective bin.

20. A semiconductor test system, comprising:

a wafer stage to hold a wafer having a plurality of light emitting devices (LEDs);

a probe test card operable to test each test field of the wafer;

a light detector integrated with the probe test card and operable to move on a track of the probe test card; and

a shield structure configured around the wafer stage to block environmental light from reaching the light detector during test operation.