METHOD FOR THE TRANSLATION OF PROGRAMS FOR RECONFIGURABLE ARCHITECTURES

• US 20110271264A1
• Filed: 07/07/2011
• Published: 11/03/2011
• Est. Priority Date: 08/16/2001
• Status: Active Grant

• Current Assignee: PACT XPP Schweiz AG
• Original Assignee: Pact XPP Technologies, AG
• Inventors: May, Frank, VORBACH, Martin, Nückel, Armin
• Granted Patent: US 8,869,121 B2
• Time in Patent Office: Days
• US Class Current: 717/149
• CPC Class Codes: G06F 8/447 Target code generation

Abstract

Data processing using multidimensional fields is described along with methods for advantageously using high-level language codes.

Claims

1-20. -20. (canceled)

21. A method for compiling high-level software programs into instruction level parallel code, comprising:

generating a code graph;

in a first analysis, analyzing the code graph for instructions that are simultaneously executable at a same level of the code graph;

in a second analysis, analyzing the code graph for instructions being simultaneously executable at different levels of the code graph; and

partitioning the code graph depending on the first and second analyses.

22. The method according to claim 21, wherein the partitioning includes mapping of parts of the code graph onto sequential processing units.

23. The method according to claim 22, wherein at least some of the sequential processing units are horizontally connected and operate on commonly received data input.

24. The method according to any one of claims 22 and 23, wherein at least some of the sequential processing units are vertically connected, and each of at least one of the sequential processing units operates on data received from at least one other of the sequential processing units.

25. The method according to claim 24, wherein code for a reconfigurable processor is produced by the method.

26. The method according to claim 24, wherein code for a field programmable gate array (FPGA) is produced by the method.

27. The method according to claim 24, wherein code for a central processing unit (CPU) is produced by the method.

28. The method according to claim 24, wherein code for a parallel processor system is produced by the method.

29. The method according to any one of claims 21 to 23, wherein code for a reconfigurable processor is produced by the method.

30. The method according to any one of claims 21 to 23, wherein code for a field programmable gate array (FPGA) is produced by the method.

31. The method according to any one of claims 21 to 23, wherein code for a central processing unit (CPU) is produced by the method.

32. The method according to any one of claims 21 to 23, wherein code for a parallel processor system is produced by the method.