NONVOLATILE SRAM/LATCH CIRCUIT USING CURRENT-INDUCED MAGNETIZATION REVERSAL MTJ

• US 20110273925A1
• Filed: 07/31/2008
• Published: 11/10/2011
• Est. Priority Date: 08/31/2007
• Status: Active Grant

• Current Assignee: Japan Science & Technology Trading Co. Limited
• Original Assignee: Tokyo Institute of Technology (National University Corporation Tokyo Institute of Technology)
• Inventors: Yamamoto, Shuichiro, Sugahara, Satoshi
• Granted Patent: US 8,295,079 B2
• Time in Patent Office: Days
• US Class Current: 365/154
• CPC Class Codes: G11C 14/0081 and the nonvolatile element is a magnetic RAM [MRAM] element or ferromagnetic cell

Abstract

The present invention is a memory circuit that includes a bistable circuit that stores data, and a ferromagnetic tunnel junction device that nonvolatilely stores the data in the bistable circuit according to a magnetization direction of a ferromagnetic electrode free layer, the data nonvolatilely stored in the ferromagnetic tunnel junction device being able to be restored in the bistable circuit. According to the present invention, writing data to and reading data from the bistable circuit can be performed at high speed. In addition, even though a power source is shut down, it is possible to restore data nonvolatilely stored in the ferromagnetic tunnel junction devices to the bistable circuit.

Claims

1. A memory circuit comprising:

a bistable circuit that stores data; and

a ferromagnetic tunnel junction device that nonvolatilely stores the data stored in the bistable circuit according to a magnetization direction of a ferromagnetic electrode free layer,

the data nonvolatilely stored in the ferromagnetic tunnel junction device being able to be restored to the bistable circuit, a first inverter circuit and a second inverter circuit being coupled in a ring shape in the bistable circuit, the ferromagnetic tunnel junction device being coupled to a node to which the first inverter circuit and the second inverter circuit are coupled and the ferromagnetic tunnel junction device being coupled between the node and a control line, and becoming a high resistance as a current flows between the node and the control line, and becoming a low resistance as a current flows to a counter direction of the current.

2. The memory circuit according to claim 1, wherein the ferromagnetic tunnel junction device changes the magnetization direction of the ferromagnetic electrode free layer by a current-induced magnetization reversal method.

5. The memory circuit according to claim 1, wherein the control line applied a high level voltage to the ferromagnetic tunnel junction device and further applied a low level voltage when storing the data from the bistable circuit to the ferromagnetic tunnel junction device.

6. The memory circuit according to claim 1, wherein the control line applies a low level or high level voltage to the ferromagnetic tunnel junction device when restoring the data from the ferromagnetic tunnel junction device to the bistable circuit.

7. The memory circuit according to claim 1 comprising a switch that is coupled between the node and the ferromagnetic tunnel junction device, and that becomes conductive when storing the data from the bistable circuit to the ferromagnetic tunnel junction device or when restoring the data from the ferromagnetic tunnel junction device to the bistable circuit.

8. The memory circuit according to claim 7, wherein the switch includes a MOSFET.

9. The memory circuit according to claim 1, wherein the node includes a first node and a second node that are complementary nodes to one another, and the ferromagnetic tunnel junction device includes a first ferromagnetic tunnel junction device which is coupled between the first node and the control line, and a second ferromagnetic tunnel junction device which is coupled between the second node and the control line.

10. The memory circuit according to claim 9, comprising:

a first switch that is provided between the first node and the first ferromagnetic tunnel junction device, and that becomes conductive when storing the data from the bistable circuit to the first ferromagnetic tunnel junction device or when restoring the data from the first tunneling junction device to the bistable circuit; and

a second switch that is provided between the second node and the second ferromagnetic tunnel junction device, and that becomes conductive when storing the data from the second ferromagnetic tunnel junction device to the bistable circuit or when restoring the data from the second ferromagnetic tunnel junction device to the bistable circuit.

11. The memory circuit according to claim 10, wherein the first switch and the second switch include a MOSFET respectively.

12. The memory circuit according to claim 9, comprising a third switch that is coupled between the control line and an electric power line which is at a low level or at a high level, the third switch becoming non-conductive when storing the data from the bistable circuit to the first ferromagnetic tunnel junction device and the second ferromagnetic tunnel junction device, and becoming conductive when restoring the data from the first ferromagnetic tunnel junction device and the second ferromagnetic tunnel junction device to the bistable circuit.

13. The memory circuit according to claim 1, comprising an input/output switch for inputting and outputting data to the node.

14. The memory circuit according to claim 13, wherein the input/output switch inputs and outputs data to the node according a level of a word line.

15. The memory circuit according to claim 1, wherein the input/output switch includes a first input/output switch for inputting and outputting data to the first node, and a second input/output switch for inputting and outputting data to the second node.

16. The memory circuit according to claim 1, wherein the ferromagnetic tunnel junction device includes a ferromagnetic electrode free layer, a ferromagnetic electrode pinned layer, and a tunnel insulation film that is provided between the ferromagnetic electrode free layer and the ferromagnetic electrode pinned layer.

3. (canceled)

4. (canceled)

17. A latch circuit comprising:

a bistable circuit that includes a first logic circuit having one or more inputs and one or more outputs and a second logic circuit having one or more inputs and one or more outputs, and stores data;

a first node to which one of outputs of the first logic circuit and one of inputs of the second logic circuit are coupled;

a second node to which one of outputs of the second logic circuit and one of inputs of the first logic circuit are coupled; and

a ferromagnetic tunnel junction device that is coupled to at least one of the first node and the second node, and nonvolatilely stores data stored in the bistable circuit according to a magnetization direction of a ferromagnetic electrode free layer,

complementary data to be stored being output from the first logic circuit and the second logic circuit to the first node and the second node respectively when storing the data from the bistable circuit to the ferromagnetic tunnel junction device, a signal that has the first logic circuit output a logic inversion of the second node to the first node being output to inputs except an input which is coupled to the second node of the first logic circuit, and a signal that has the second logic circuit output a logic inversion of the first node to the second node being output to inputs except an input which is coupled to the first node of the second logic circuit when restoring the data from the ferromagnetic tunnel junction device to the bistable circuit, the ferromagnetic tunnel junction device being coupled to at least one node of the first node and the second node, and the ferromagnetic tunnel junction device being coupled between the at least one node and a control line, becoming a high resistance as a current flows between the at least one node and the control line, and becoming a low resistance as a current flows to a counter direction of the current flowing between the at least one node and the control line.

19. The letch circuit according to claim 17, wherein the ferromagnetic tunnel junction device changes the magnetization direction of the ferromagnetic electrode free layer by a current-induced magnetization reversal method.

22. The latch circuit according to claim 17, wherein the control line applies a high level voltage to the ferromagnetic tunnel junction device, and further applies a low level voltage when storing the data from the bistable circuit to the ferromagnetic tunnel junction device.

23. The latch circuit according to claim 17, wherein the control line applies a low level or high level voltage to the ferromagnetic tunnel junction device when restoring the data from the ferromagnetic tunnel junction device to the bistable circuit.

24. The latch circuit according to claim 17 comprising a switch that is coupled between the at least one node and the ferromagnetic tunnel junction device, and becomes conductive when storing the data from the bistable circuit to the ferromagnetic tunnel junction device or when restoring the data from the ferromagnetic tunnel junction device to the bistable circuit.

25. The memory circuit according to claim 24, wherein the switch includes a MOSFET.

26. The latch circuit according to claim 17, wherein the ferromagnetic tunnel junction device includes a first ferromagnetic tunnel junction device that is coupled between the first node and the control line, and a second ferromagnetic tunnel junction device that is coupled between the second node and the control line.

27. The latch circuit according to claim 26, comprising:

a first switch that is provided between the first node and the first ferromagnetic tunnel junction device, and becomes conductive when storing the data from the bistable circuit to the first ferromagnetic tunnel junction device or when restoring the data from the first ferromagnetic tunnel junction device to the bistable circuit; and

a second switch that is provided between the second node and the second ferromagnetic tunnel junction device, and becomes conductive when storing the data to the second ferromagnetic tunnel junction device or when restoring the data to the bistable circuit.

28. The latch circuit according to claim 26, wherein the first switch and the second switch include a MOSFET respectively.

29. The latch circuit according to claim 26 comprising a third switch that is coupled between the control line and an electric power line which is at a low level or at a high level, the third switch becoming non-conductive when storing the data from the bistable circuit to the first ferromagnetic tunnel junction device and the second ferromagnetic tunnel junction device, and becoming conductive when restoring the data from the first ferromagnetic tunnel junction device and the second ferromagnetic tunnel junction device to the bistable circuit.

30. The latch circuit according to claim 17, wherein that-the ferromagnetic tunnel junction device includes a ferromagnetic electrode free layer, a ferromagnetic electrode pinned layer, and a tunnel insulation film provided between the ferromagnetic electrode free layer and the ferromagnetic electrode pinned layer.

18. A latch circuit comprising:

a bistable circuit that stores data, and where a first inverter circuit and a second inverter circuit are coupled in a ring shape;

a first node and a second node to which the first inverter circuit and the second inverter circuit are coupled, and that are a complementary node to one another;

a first input switch for writing the data to the bistable circuit from an input line;

a second input switch that behaves in a complementary style to the first input switch, and holds data of the bistable circuit; and

a ferromagnetic tunnel junction device that nonvolatilely stores data stored in the bistable circuit according to a magnetization direction of a ferromagnetic electrode free layer,

data nonvolatilely stored in the ferromagnetic tunnel junction device being able to restored to the bistable circuit, the ferromagnetic tunnel junction device being coupled to at least one node of the first node and the second node, and the ferromagnetic tunnel junction device being coupled between the at least one node and a control line, becoming a high resistance as a current flows between the at least one node and the control line, and becoming a low resistance as a current flows to a counter direction of the current flowing between the at least one node and the control line.

20. (canceled)

21. (canceled)

31. A flip-flop circuit comprising:

latch circuit which includes;

a bistable circuit that includes a first logic circuit having one or more inputs and one or more outputs and a second logic circuit having one or more inputs and one or more outputs, and stores data;

a first node to which one of the outputs of the first logic circuit and one of inputs of the second logic circuit are coupled;

a second node to which one of outputs of the second logic circuit and one of the inputs of the first logic circuit are coupled;

a ferromagnetic tunnel junction device that is coupled to at least one of the first node and the second node, and nonvolatiley stores data stored in the stored in the bistable circuit according to a magnetization direction of a ferromagnetic electrode free layer, complementary data to be stored being output from the first logic circuit and the second logic circuit to the first node and the second node respectively when storing the data from the bistable circuit to the ferromagnetic tunnel junction device, a signal that has the first logic circuit output a logic inversion of the second node to the first node being output to inputs except an input which is coupled to the second node of the first logic circuit, and a signal that has the second logic circuit output a logic is inversion of the first node to the second node being output to inputs except an input which is coupled to the first node of the second logic circuit when restoring the data from the ferromagnetic tunnel junction device to the bistable circuit, the ferromagnetic tunnel junction device being coupled to at least one node of the first node and the second node, and the ferromagnetic tunnel junction device being coupled between the at least one node and a control line, becoming a high resistance as a current flows between the at least one node and the control line, and becoming a low resistance as a current flows to a counter direction of the current flowing between the at least one node and the control line.