LINEARIZATION SYSTEMS AND METHODS FOR VARIABLE ATTENUATORS

• US 20110285481A1
• Filed: 05/21/2010
• Published: 11/24/2011
• Est. Priority Date: 05/21/2010
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd., Georgia Tech Research Corporation (University System of Georgia)
• Original Assignee: Samsung Electronics Co. Ltd., Georgia Tech Research Corporation (University System of Georgia)
• Inventors: Huang, Yanyu, Lee, Chang-Ho, Woo, Wangmyong, Laskar, Joy
• Granted Patent: US 8,179,205 B2
• Time in Patent Office: Days
• US Class Current: 333/81.R
• CPC Class Codes: H01P 1/22 Attenuating devices dissipative terminating devices H01P1/26
• CPC Class Codes: H03G 1/007 using FET type devices
• CPC Class Codes: H03H 11/245 using field-effect transistor

Abstract

Systems and methods for provided for linearization systems and methods for variable attenuators. The variable attenuators can include series transistors along a main signal path from the input to output, as well as shunt transistors. A bootstrapping body bias circuit can be used with one or of the series transistors to allow the body of a connected transistor to swing responsive to a received RF input signal. As the RF signal increases and affects the gate-to-source voltage difference of a transistor, a bootstrapping body bias circuit can adaptively adjust the threshold voltage of the connected transistor and compensate the channel resistance variation resulting from gate-to-source voltage swing. The bootstrapping body bias circuit can be implemented using passive elements, active elements, or a combination thereof.

Claims

1. A variable attenuator, comprising:

at least one series transistor, including a first series transistor, provided in main signal path between an input terminal and an output terminal, the input terminal for receiving a RF input signal and the output terminal for outputting an attenuated RF output signal, wherein the first series transistor includes at least a first drain terminal, a first source terminal, and a first body terminal, wherein the first drain terminal and the first source terminal are part of the main signal path;

at least one first shunt transistor connected between the input terminal and ground;

at least one second shunt transistor connected between the output terminal and ground;

at least one bootstrapping body bias circuit, including a first bootstrapping body bias circuit to connect either the first drain terminal or the first source terminal to the first body terminal, wherein each bootstrapping body bias circuit is associated with a respective resistance or impedance.

2. The variable attenuator of claim 1, wherein each bootstrapping body bias circuit includes at least one of:

(i) an inductor, (ii) a capacitor, or (iii) a resistor.

3. The variable attenuator of claim 1, wherein each bootstrapping body bias circuit includes a variable resistance element, wherein a respective resistance or impedance of the variable resistance element is adjustable based upon a control signal provided to the variable resistance element.

4. The variable attenuator of claim 3, wherein the variable resistance element is a transistor.

5. The variable attenuator of claim 4, wherein the transistor is a field effect transistor (FET) or a bipolar junction transistor (BJT).

6. The variable attenuator of claim 1, wherein the first bootstrapping body bias circuit is operative to couple at least a portion of the received RF input signal from the first drain terminal or first source terminal to the first body terminal.

7. The variable attenuator of claim 1,

wherein the at least one first shunt transistor includes at least a second drain terminal and a second source terminal, wherein the second drain terminal is connected to the input terminal, and the second source terminal is connected to ground, and

wherein the at least one second shunt transistor includes at least a third drain terminal and a third source terminal, wherein the third drain terminal is connected to the output terminal, and the third source terminal is connected to ground.

8. The variable attenuator of claim 1, wherein the at least one series transistor further includes a second series transistor having a second drain terminal, a second source terminal, and a second body terminal, wherein the first drain terminal is connected to the input terminal, the first source terminal is connected to the second drain terminal, and the second source terminal is connected to either the output terminal or a third drain of a third series transistor of the at least one series transistor, and further comprising:

at least one third shunt transistor connected between an intersection of the first source terminal and the second drain terminal and ground; and

a second bootstrapping body bias circuit to connect the second body substrate to either (i) the second drain terminal or the second source terminal, or (ii) the first bootstrapping body bias circuit.

9. The variable attenuator of claim 1, wherein the at least one series transistor, the at least one first shunt transistor, and the at least one second shunt transistor includes a respective gate terminal for receiving a respective control voltage to adjust a respective resistance of the respective series transistor, first shunt transistor, and second shunt transistor.

10. The variable attenuator of claim 1, wherein during a low attenuation setting, the respective control signals of the at least one first and second shunt transistors are set to a first low voltage, and the respective control signal of the at least one series transistor is set to a first high voltage;

and wherein during a high attenuation setting, the respective control signals of the at least one first and second shunt transistors are set to a second high voltage, and the respective control signal of the at least one series transistor is set to a second low voltage.

11. A method for a variable attenuator, comprising:

providing at least one series transistor, including a first series transistor, along a main signal path between an input terminal and an output terminal, the input terminal for receiving a RF input signal and the output terminal for outputting an attenuated RF output signal, wherein the first series transistor includes at least a first drain terminal, a first source terminal, and a first body terminal, wherein the first drain terminal and the first source terminal are part of the main signal path;

connecting at least one first shunt transistor between the input terminal and ground;

connecting at least one second shunt transistor between the output terminal and ground; and

providing at least one bootstrapping body bias circuit, including a first bootstrapping body bias circuit to connect either the first drain terminal or the first source terminal to the first body terminal, wherein each bootstrapping body bias circuit is associated with a respective resistance or impedance.

12. The method of claim 11, wherein each bootstrapping body bias circuit includes at least one of:

(i) an inductor, (ii) a capacitor, or (iii) a resistor.

13. The method of claim 11, wherein each bootstrapping body bias circuit includes a variable resistance element, wherein a respective resistance or impedance of the variable resistance element is adjustable based upon a control signal provided to the variable resistance element.

14. The method of claim 13, wherein the variable resistance element is a transistor.

15. The method of claim 14, wherein the transistor is a field effect transistor (FET) or a bipolar junction transistor (BJT).

16. The method of claim 11, wherein the first bootstrapping body bias circuit is operative to couple at least a portion of the received RF input signal from the first drain terminal or first source terminal to the first body terminal.

17. The method of claim 11,

wherein the at least one first shunt transistor includes at least a second drain terminal and a second source terminal, wherein the second drain terminal is connected to the input terminal, and the second source terminal is connected to ground, and

wherein the at least one second shunt transistor includes at least a third drain terminal and a third source terminal, wherein the third drain terminal is connected to the output terminal, and the third source terminal is connected to ground.

18. The method of claim 11, wherein the at least one series transistor further includes a second series transistor having a second drain terminal, a second source terminal, and a second body terminal, wherein the first drain terminal is connected to the input terminal, the first source terminal is connected to the second drain terminal, and the second source terminal is connected to either the output terminal or a third drain of a third series transistor of the at least one series transistor, and further comprising:

connecting at least one third shunt transistor between an intersection of the first source terminal and the second drain terminal and ground; and

providing a second bootstrapping body bias circuit to connect the second body substrate to either (i) the second drain terminal or the second source terminal, or (ii) the first bootstrapping body bias circuit.

19. The method of claim 11, wherein the at least one series transistor, the at least one first shunt transistor, and the at least one second shunt transistor includes a respective gate terminal for receiving a respective control voltage to adjust a respective resistance of the respective series transistor, first shunt transistor, and second shunt transistor.

20. The method of claim 11, wherein during a low attenuation setting, the respective control signals of the at least one first and second shunt transistors are set to a first low voltage, and the respective control signal of the at least one series transistor is set to a first high voltage;

and wherein during a high attenuation setting, the respective control signals of the at least one first and second shunt transistors are set to a second high voltage, and the respective control signal of the at least one series transistor is set to a second low voltage.