SYSTEM INCLUDING A FINE-GRAINED MEMORY AND A LESS-FINE-GRAINED MEMORY

• US 20110289263A1
• Filed: 05/31/2011
• Published: 11/24/2011
• Est. Priority Date: 05/30/2007
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Enterprise IP LLC (Western Digital Corporation)
• Inventors: Bruening, Ulrich, Cohen, Earl T., McWilliams, Thomas M., Bodwin, James M.
• Granted Patent: US 8,244,969 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0284 Multiple user address space allocation, e.g. using different base addresses interprocessor communication G06F15/163
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/0806 Multiuser, multiprocessor or multiprocessing cache systems
• CPC Class Codes: G06F 2212/1044 Space efficiency improvement
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/2542 Non-uniform memory access [NUMA] architecture
• CPC Class Codes: G06F 2212/401 Compressed data
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A data processing system includes one or more nodes, each node including a memory sub-system. The sub-system includes a fine-grained, memory, and a less-fine-grained (e.g., page-based) memory. The fine-grained memory optionally serves as a cache and/or as a write buffer for the page-based memory. Software executing on the system uses a node address space which enables access to the page-based memories of all nodes. Each node optionally provides ACID memory properties for at least a portion of the space. In at least a portion of the space, memory elements are mapped to locations in the page-based memory. In various embodiments, some of the elements are compressed, the compressed elements are packed into pages, the pages are written into available locations in the page-based memory, and a map maintains an association between the some of the elements and the locations.

Claims

1-42. -42. (canceled)

43. A memory system comprising:

a non-volatile memory comprising a plurality of pages, where units of the memory smaller than one of the pages of the memory are not independently writable, and where each of the pages of the memory comprises a respective user-accessible portion;

a map configured to associate respective element identifiers of each of a plurality of elements with a respective physical location of the element in the memory, where the respective physical location comprises an address of a respective one of the pages of the memory and a respective offset within the respective page of the memory;

a coalescing buffer comprising a plurality of pages, a size of each of the pages of the coalescing buffer being sufficient to contain the respective user-accessible portion of one of the pages of the memory;

wherein the memory system is configured to write a first one of the elements to the memory by

storing the first element in a first portion of a particular one of the pages of the coalescing buffer,

copying the particular page of the coalescing buffer to a particular one of the pages of the memory, and

updating the map so that the address of the respective page of the respective physical location of the first element is an address of the particular page of the memory, and so that the respective offset of the respective physical location of the first element is according to the first portion of the particular page of the coalescing buffer; and

wherein the memory system is further configured, subsequent to the storing of the first element in the particular page of the coalescing buffer and prior to the copying of the particular page of the coalescing buffer to the particular page of the memory, to store a second one of the elements in a second portion of the particular page of the coalescing buffer, the second element different from the first element, the second portion separate from the first portion.

44. The system of claim 43, wherein the elements are not all of a same size.

45. The system of claim 44, wherein the first element and the second element are different in size.

46. The system of claim 43, wherein the memory system is further configured, in conjunction with the storing of the first element in the particular page of the coalescing buffer, to store a respective error detecting code covering the first element in the particular page of the coalescing buffer.

47. The system of claim 46, wherein the respective error detecting code is a Cyclic Redundancy Check (CRC).

48. The system of claim 46,

wherein the memory system is further configured to write the first element to the memory by copying the particular page of the coalescing buffer to the respective user-accessible portion of the particular page of the memory;

and

wherein the respective user-accessible portion of the particular page of the memory is enabled to store the respective error detecting code covering the first element along with the first element.

49. The system of claim 48,

wherein each of the pages of the memory is associated with a respective overhead portion distinct from the respective user-accessible portion;

and

wherein the respective overhead portion of the particular page of the memory is enabled to store an error correcting code protecting at least some of the respective user-accessible portion of the particular page.

50. The system of claim 49, wherein each of the pages of the memory further comprises the respective overhead portion.

51. The system of claim 49, wherein a block of the memory containing the particular page of the memory comprises the respective overhead portion of the particular page of the memory.

52. The system of claim 51, wherein the respective user-accessible portion of the particular page of the memory is all of the particular page of the memory.

53. The system of claim 49, wherein, subsequent to the copying of the particular page of the coalescing buffer to the respective user-accessible portion of the particular page of the memory, the error correcting code is enabled to protect the first element and the second element.

54. The system of claim 49, wherein the memory system is further configured to read the first element by

using the map to associate the respective element identifier of the first element with the respective physical location of the first element, the respective page of the respective physical location of the first element being the particular page of the memory, and

retrieving a portion less than all of the respective user-accessible portion of the particular page of the memory according to the respective offset of the respective physical location of the first element.

55. The system of claim 54,

wherein the portion less than all is a first portion less than all;

and

wherein a second portion less than all of the respective user-accessible portion of the particular page of the memory is enabled to store at least a part of the second element, the second portion less than all distinct from the first portion less than all.

56. The system of claim 55, wherein the first element and the second element are different in size.

57. The system of claim 54,

wherein the portion less than all of the particular page of the memory is enabled to store the respective error detecting code covering the first element;

and

wherein the memory system is further configured to read the first element by detecting a presence of an error in the first element as stored in the portion less than all using the respective error detecting code as stored in the portion less than all.

58. The system of claim 57, wherein the memory system is further configured, in response to the detecting of the presence of the error in the first element as stored in the portion less than all, to

retrieve a second portion of the memory, the second portion comprising the error correcting code, and

use the error correcting code to correct the error in the first element as stored in the portion less than all.

59. The system of claim 46, wherein the memory system is further configured to read the first element from the first portion of the particular page of the coalescing buffer.

60. The system of claim 59, wherein the memory system is enabled to use the coalescing buffer as a cache of the memory.

61. The system of claim 43, wherein the memory system is further configured to determine the particular page of the coalescing buffer.

62. The system of claim 61, wherein the memory system is further configured to determine the particular page of the coalescing buffer according to a respective expected write frequency associated with each of the pages of the coalescing buffer.

63. The system of claim 61, wherein the memory system is further configured to determine the particular page of the coalescing buffer according to a respective expected write frequency associated with the first element.

64. The system of claim 61,

wherein the memory comprises a plurality of shards, each of the shards comprising a respective subset of the pages of the memory;

and

wherein the memory system is further configured to determine the particular page of the coalescing buffer according to the shard containing the particular page of the memory.

65. The system of claim 43,

wherein the particular page of the memory is a first page of the memory;

wherein the memory system is further configured to coalesce a second one of the pages of the memory, the second page of the memory different from the first page of the memory, by

reading, prior to the storing of the first element in the first page of the coalescing buffer, the first element from the second page of the memory, and

erasing, subsequent to the reading of the first element, a block of the memory containing the second page of the memory.

66. The system of claim 65, wherein, prior to the reading of the first element from the second page of the memory, the map is configured so that the address of the respective page of the respective physical location of the first element is an address of the second page of the memory, and so that the respective offset of the respective physical location of the first element is an offset within the second page of the memory.

67. The system of claim 66, wherein the offset within the second page is different from the respective offset according to the first portion of the particular page of the coalescing buffer.

68. The system of claim 43, wherein each of the elements smaller in size than one half of a size of one of the pages of the memory is enabled to be stored along with a respective error detecting code in the respective user-accessible portion of one of the pages of the memory.

69. The system of claim 68, wherein each of the elements larger in size than a specified minimum size and smaller in size than one half of a size of one of the pages of the memory is enabled to be stored along with a respective error detecting code in the respective user-accessible portions of a contiguous, with respect to addresses of the memory, pair of the pages of the memory.

70. The system of claim 68, wherein the memory system is further configured to compute the respective error detecting code.

71. The system of claim 68,

wherein each of the pages of the memory is associated with a respective overhead portion, the respective overhead portion distinct from the respective user-accessible portion;

and

wherein the respective overhead portion of the particular page of the memory is enabled to store an error correcting code protecting the respective user-accessible portion of the particular page.

72. The system of claim 71, wherein each of the pages of the memory further comprises the respective overhead portion.

73. The system of claim 71,

wherein the memory comprises a plurality of blocks, each of the blocks comprising a respective one or more of the pages of the memory;

and

wherein one of the blocks of the memory comprising the particular page of the memory comprises the respective overhead portion of the particular page of the memory.

74. The system of claim 73, wherein the respective user-accessible portion of the particular page of the memory is all of the particular page of the memory.

75. The system of claim 73, wherein a minimum erasable unit of the memory is one of the blocks of the memory.

76. The system of claim 43, wherein the memory is organized as a plurality of erasable blocks, each of the blocks comprising a respective one or more of the pages of the memory.

77. The system of claim 43,

wherein the map comprises a plurality of entries, each of elements corresponding to a distinct one of the entries, the respective element identifier associated with the corresponding entry;

and

wherein each of the entries is enabled to store the respective physical location of the one of the elements corresponding to the entry.

78. The system of claim 43, wherein the respective offset is an index within the respective page of the memory, the index having a granularity of no more than 64 bytes.

79. The system of claim 78, wherein the respective offset is an index within the respective page of the memory, the index having a granularity of no more than eight bytes.

80. The system of claim 43, further comprising a Direct Memory Access (DMA) controller, the DMA controller enabled to perform the copying of the particular page of the coalescing buffer to the particular page of the memory.

81. The system of claim 43,

wherein the memory is part of a particular one or more semiconductor devices;

and

wherein the coalescing buffer is part of one or more semiconductor devices separate from the particular semiconductor devices.

82-118. -118. (canceled)

119. A method comprising:

coalescing a first one of a plurality of logical partitions stored in a first one of a plurality of pages of a non-volatile, less-fine-grained memory and a second one of the logical partitions stored in a second one of the pages of the less-fine-grained memory into separate regions in a particular page of a write buffer in a volatile, fine-grained memory, where each of the pages of the less-fine-grained memory is enabled to store a respective two or more of the logical partitions, and where a minimum writable unit of the less-fine-grained memory is one of the pages of the less-fine-grained memory;

writing, subsequent to the coalescing, the particular page of the write buffer to a third one of the pages of the less-fine-grained memory, where the first page, the second page, and the third page are all different ones of the pages of the less-fine-grained memory; and

maintaining a map comprising a plurality of entries, each of the entries associating a respective one of a plurality of elements with a respective one of the logical partitions of a respective one of the pages of the less-fine-grained memory, and where prior to the writing, a first one of the elements is associated with the first logical partition via a first one of the entries of the map, and a second one of the elements is associated with the second logical partition via a second one of the entries of the map.

120. The method of claim 119, wherein the less-fine-grained memory is a solid-state memory.

121. The method of claim 119, wherein a size of the first logical partition is different from a size of the second logical partition.

122. The method of claim 119, wherein the maintaining comprises updating the first entry to associate the first element with a third one of the logical partitions stored in the third page of the less-fine-grained memory.

123. The method of claim 122, wherein the updating the first entry comprises updating an offset stored in the first entry to be an offset of the third logical partition stored in the third page of the less-fine-grained memory.

124. The method of claim 123,

wherein prior to the updating the first entry, the offset stored in the first entry is an offset of the first logical partition stored in the first page of the less-fine-grained memory;

and

wherein the offset of the third logical partition is different from the offset of the first logical partition.

125. The method of claim 123, wherein the offset stored in the first entry has a granularity of no more than 64 bytes.

126. The method of claim 123, wherein the offset stored in the first entry has a granularity of no more than eight bytes.

127. The method of claim 122, further comprising:

reading, prior to the coalescing, the first element from the first page of the less-fine-grained memory; and

reading, subsequent to the writing, the first element from the third page of the less-fine-grained memory.

128. The method of claim 122,

wherein each of the first logical partition, the second logical partition, and the third logical partition stores a respective error detecting code;

and

wherein the writing comprising storing in the third page of the less-fine-grained memory a respective error correcting code protecting contents of the third page of the less-fine-grained memory including the third logical partition, and where the respective error correcting code of the third page of the less-fine-grained memory is different from the respective error detecting code of the third logical partition.

129. The method of claim 119, wherein the particular page of the write buffer is one of a plurality of pages of the write buffer.

130. The method of claim 119, wherein the first logical partition stores data of the first element in a compressed form.

131. The method of claim 130, wherein the first logical partition further stores a header of the compressed data of the first element.

132. The method of claim 131, wherein the header comprises a type of compression used to produce the compressed form.

133. The method of claim 131, wherein the header comprises a size of the compressed data of the first element.

134. The method of claim 119, wherein the coalescing comprises storing at least a portion of the first logical partition into the particular page of the write buffer, and subsequently storing at least a portion of the second logical partition into the particular page of the write buffer.

135. The method of claim 134, wherein the coalescing further comprises:

computing a respective error detecting code for each of the at least a portion of the first logical partition and the at least a portion of the second logical partition; and

storing the respective error detecting codes into the particular page of the write buffer.

136. The method of claim 134,

wherein the first logical partition comprises a respective error detecting code;

and

wherein the at least a portion of the first logical partition is all of the first logical partition.

137. The method of claim 119, wherein, prior to the coalescing, the first page of the less-fine-grained memory stores at least two of the logical partitions.

138. The method of claim 119, further comprising, subsequent to the coalescing, erasing a block of the less-fine-grained memory containing the first page of the less-fine-grained memory.

139. The method of claim 138, further comprising, subsequent to the erasing, adding the block to a free list.

140. The method of claim 139, further comprising determining the third page of the less-fine-grained memory based, at least in part, on the free list.

141. The method of claim 119, further comprising, in event of a power disruption of a primary power source coupled to the fine-grained memory, powering the write buffer via a back-up power source.

142. The method of claim 141, further comprising, in the event of the power disruption being subsequent to the coalescing and prior to the writing, saving the particular page of the write buffer to a determined one of the pages of the less-fine-grained memory.

143. The method of claim 142, wherein the determined page of the less-fine-grained memory is the third page of the less-fine-grained memory.