DEVICE AND METHOD FOR FABRICATING THIN SEMICONDUCTOR CHANNEL AND BURIED STRAIN MEMORIZATION LAYER

• US 20110291100A1
• Filed: 05/28/2010
• Published: 12/01/2011
• Est. Priority Date: 05/28/2010
• Status: Active Grant

• Current Assignee: Alsephina Innovations Inc. (Quarterhill Inc. (f/k/a Wi-LAN Inc.))
• Original Assignee: International Business Machines Corporation
• Inventors: Khakifirooz, Ali, Shahidi, Ghavam G., Doris, Bruce B., Kulkarni, Pranita, CHENG, KANGGUO
• Granted Patent: US 9,461,169 B2
• Time in Patent Office: Days
• US Class Current: 257/66
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02664 Aftertreatments planarisation in general H01L21/304
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/7847 using a memorization technique, e.g. re-crystallization under strain, bonding on a substrate having a thermal expansion coefficient different from the one of the region
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A device and method for inducing stress in a semiconductor layer includes providing a substrate having a dielectric layer formed between a first semiconductor layer and a second semiconductor layer and processing the second semiconductor layer to form an amorphized material. A stress layer is deposited on the first semiconductor layer. The wafer is annealed to memorize stress in the second semiconductor layer by recrystallizing the amorphized material.

Claims

1. A method for inducing stress in a semiconductor layer, comprising:

providing a substrate having a dielectric layer formed between a first semiconductor layer and a second semiconductor layer;

processing the second semiconductor layer to form an amorphized material;

depositing a stress layer on the first semiconductor layer; and

annealing the wafer to memorize stress in the second semiconductor layer by recrystallizing the amorphized material.

2. The method as recited in claim 1, further comprising removing the stress layer.

3. The method as recited in claim 1, further comprising forming a device having a channel in the first semiconductor layer, wherein the memorized stress of the second semiconductor layer provides stress in the channel.

4. The method as recited in claim 1, wherein processing the second semiconductor layer includes implanting ions in the second semiconductor layer to form the amorphized material.

5. The method as recited in claim 4, wherein implanting ions includes implanting at least one of Ge, Si, Ar, N and Xe.

6. The method as recited in claim 1, wherein depositing a stress layer includes depositing a silicon nitride layer.

7. The method as recited in claim 1, wherein depositing a stress layer includes adjusting deposition parameters to adjust a stress provided by the stress layer.

8. The method as recited in claim 1, wherein depositing a stress layer includes patterning the stress layer.

9. The method as recited in claim 8, wherein patterning the stress layer includes applying the stress layer in first regions while eliminating the stress layer from second regions.

10. The method as recited in claim 9, wherein the stress layer in first regions applies stress to enhance drive current and the second regions are not stressed.

11. The method as recited in claim 8, wherein patterning the stress layer includes applying a first stress layer in first regions and a second stress layer in second regions.

12. The method as recited in claim 11, wherein the first stress layer provides a first stress in the first regions and the second stress layer provides a second stress in the second regions.

13. A method for inducing stress in a semiconductor layer, comprising:

providing a substrate having a dielectric layer formed between a first semiconductor layer and a second semiconductor layer;

forming a gate structure for a transistor device on the first semiconductor layer;

implanting ions in the second semiconductor layer to form an amorphized material in areas not protected by the gate stack;

depositing a stress layer on the gate structure and the first semiconductor layer; and

annealing the wafer to memorize stress in the second semiconductor layer by recrystallizing the amorphized material.

14. The method as recited in claim 13, wherein the transistor device has a channel in the first semiconductor layer such that the memorized stress of the second semiconductor layer provides stress in the channel.

15. The method as recited in claim 13, wherein implanting ions includes implanting at least one of Ge, Si, Ar, N and Xe.

16. The method as recited in claim 13, wherein depositing a stress layer includes depositing a silicon nitride layer.

17. The method as recited in claim 13, wherein depositing a stress layer includes adjusting deposition parameters to adjust a stress provided by the stress layer.

18. The method as recited in claim 13, wherein depositing a stress layer includes patterning the stress layer.

19. The method as recited in claim 18, wherein patterning the stress layer includes applying the stress layer in first regions while eliminating the stress layer from second regions.

20. The method as recited in claim 19, wherein the stress layer in first regions applies stress to enhance drive current and the second regions are not stressed.

21. The method as recited in claim 18, wherein patterning the stress layer includes applying a first stress layer in first regions and a second stress layer in second regions.

22. The method as recited in claim 21, wherein the first stress layer provides a first stress in the first regions and the second stress layer provides a second stress in the second regions.

23. A semiconductor device, comprising:

a substrate having a dielectric layer formed between a first semiconductor layer and a second semiconductor layer;

a gate structure for a transistor device formed on the first semiconductor layer; and

a memorization layer formed from a recrystallized material of the second semiconductor layer such that stress induced in the recrystallized material induces stress to a device channel formed below the gate structure in the first semiconductor layer.

24. The device as recited in claim 23, wherein the semiconductor device includes n-type and p-type polarity devices and the semiconductor device includes only one of n-type polarity devices and p-type polarity device having a stressed channel in the first semiconductor layer from the memorization layer.

25. The device as recited in claim 23, wherein the semiconductor device includes n-type and p-type polarity devices and the n-type polarity devices have a different amount of stress than the p-type polarity devices in a stressed channel in the first semiconductor layer.