BELIEF PROPAGATION PROCESSOR
First Claim
Patent Images
1. An analog processor comprising:
- a first memory module for storing a first set of storage values in respective storage elements each representing a respective input to the processor;
a second memory module for storing a second set of storage values in analog form in respective storage, the second set of storage values including intermediate values determined during operation of the processor;
an analog computation module coupled to the first and the second memory modules, the processor being configurable such that in each of a plurality of operation cycles the analog module determines values for at least some of the second set of storage values based on at least some of the first and the second sets of storage values; and
an output module for generating a set of outputs from at least some of the second set of storage values.
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Abstract
A processor includes a first memory module for storing a first set of storage values each representing a respective input, and a second memory module for storing a second set of storage values in analog form. An analog module is coupled to the first and the second memory modules. The analog module is configured to, in each operation cycle of at least one iteration, update at least some of the second set of storage values based on the first and the second sets of storage values. An output module is for generating a set of outputs from at least some of the second set of storage values.
8 Citations
30 Claims
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1. An analog processor comprising:
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a first memory module for storing a first set of storage values in respective storage elements each representing a respective input to the processor; a second memory module for storing a second set of storage values in analog form in respective storage, the second set of storage values including intermediate values determined during operation of the processor; an analog computation module coupled to the first and the second memory modules, the processor being configurable such that in each of a plurality of operation cycles the analog module determines values for at least some of the second set of storage values based on at least some of the first and the second sets of storage values; and an output module for generating a set of outputs from at least some of the second set of storage values. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 24, 25)
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- 22. The processor of claim 22 wherein the analog processing elements include elements that represent soft logical operations.
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26. A decoder comprising:
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a first memory for storing code data having a length in bits; a second memory for storing intermediate data in analog form; an analog decoder core coupled to the first memory and to the second memory, the decoder core having an input length less than the length of the code data and an output length less than a number of constraints represented in the code data; a controller for, in each of a plurality of cycles, coupling the inputs of the decoder code to selected values from the first and the second memories, and coupling outputs of the decoder core for storage in the second memory; and an output section coupled to the second memory for providing decoded data based on values stored in the second memory. - View Dependent Claims (27)
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28. A decoding method comprising:
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in each of a plurality of cycles of a decoding operation, applying a portion of code data and a portion of an intermediate value data to an analog decoder core, and storing an output of the decoder coder in an analog storage for the intermediate data; and combining data, including intermediate value data from the analog storage, to form decoded data representing an error correction of the code data. - View Dependent Claims (29, 30)
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Specification