INTEGRATED CIRCUITS AND METHODS OF FORMING THE SAME

• US 20110298551A1
• Filed: 06/08/2010
• Published: 12/08/2011
• Est. Priority Date: 06/08/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: KUO, Chin-Wei, CHEN, Ming-Fa, LIU, Sally, YEN, Hsiao-Tsung, HU, Hsien-Pin, LU, Jhe-Ching
• Granted Patent: US 8,362,591 B2
• Time in Patent Office: Days
• US Class Current: 331/117.FE
• CPC Class Codes: H01L 27/016 Thin-film circuits
• CPC Class Codes: H01L 29/93 Variable capacitance diodes, e.g. varactors

Abstract

A three-dimensional integrated circuit includes a semiconductor substrate where the substrate has an opening extending through a first surface and a second surface of the substrate and where the first surface and the second surface are opposite surfaces of the substrate. A conductive material substantially fills the opening of the substrate to form a conductive through-substrate-via (TSV). An active circuit is disposed on the first surface of the substrate, an inductor is disposed on the second surface of the substrate and the TSV is electrically coupled to the active circuit and the inductor. The three-dimensional integrated circuit may include a varactor formed from a dielectric layer formed in the opening of the substrate such that the conductive material is disposed adjacent the dielectric layer and an impurity implanted region disposed surrounding the TSV such that the dielectric layer is formed between the impurity implanted region and the TSV.

Claims

1. A varactor for a voltage-controlled oscillator (VCO), comprising:

a) a semiconductor substrate having an opening extending through a first surface and a second surface of the substrate, wherein the first surface and the second surface are opposite surfaces of the substrate;

b) a dielectric layer disposed on a side surface in the opening;

c) a conductive material formed on the dielectric layer and substantially filling the opening to form a conductive through-substrate-via (TSV); and

d) an impurity implanted region disposed in the substrate surrounding the TSV and the dielectric layer.

2. The varactor of claim 1, wherein the impurity implanted region is a deep n-well.

3. The varactor of claim 1, wherein the substrate comprises a material selected from the group consisting of:

Group IV elemental or compound semiconductors and Group III-V semiconductors.

4. The varactor of claim 3, wherein the substrate comprises silicon.

5. The varactor of claim 1, further comprising:

a bias terminal electrically coupled to the TSV and a bias voltage source.

6. The varactor of claim 5, wherein the bias voltage source is configured to provide a bias voltage substantially between −

6 and −

14 volts.

7. The varactor of claim 1, further comprising:

a bias terminal electrically coupled to the impurity implanted region and a bias voltage source.

8. A three-dimensional integrated circuit, comprising:

a) a semiconductor substrate, the substrate having an opening extending through a first surface and a second surface of the substrate, wherein the first surface and the second surface are opposite surfaces of the substrate;

b) a conductive material substantially filling the opening to form a conductive through-substrate-via (TSV);

c) an active circuit disposed on the first surface of the substrate; and

d) an inductor disposed on the second surface of the substrate;

wherein the TSV is electrically coupled to the active circuit and the inductor.

9. The three-dimensional integrated circuit of claim 8, further comprising

a dielectric layer formed in the opening, wherein the conductive material is disposed adjacent the dielectric layer.

10. The three-dimensional integrated circuit of claim 9, further comprising:

an impurity implanted region disposed surrounding the TSV, and wherein the dielectric layer is formed between the impurity implanted region and the TSV.

11. The three-dimensional integrated circuit of claim 10, wherein the impurity implanted region is a deep n-well.

12. The three-dimensional integrated circuit of claim 11, wherein the TSV, the dielectric layer and the deep n-well form a first varactor.

13. The three-dimensional integrated circuit of claim 12, wherein the three-dimensional integrated circuit is a voltage controlled oscillator (VCO).

14. The three-dimensional integrated circuit of claim 12, further comprising a second varactor electrically coupled in parallel to the first varactor.

15. The three-dimensional integrated circuit of claim 12, wherein the first varactor is electrically coupled in parallel to one or more of a capacitor selected from the group consisting of:

a second varactor, metal-oxide-metal (MOM) capacitor, metal-insulator metal (MIM) capacitor or combinations thereof.

16. The three-dimensional integrated circuit of claim 12, further comprising:

a bias terminal electrically coupled to the first varactor and a bias voltage source.

17. A method of forming a varactor, comprising:

a) providing a substrate;

b) forming an opening in a first surface of the substrate

c) implanting impurities in a side wall surrounding the opening;

d) forming a dielectric layer on the implanted side wall in the opening; and

e) substantially filling the opening with a conductive material.

18. The method of claim 17, wherein the step of implanting comprises tilted n-type ion implanting.

19. The method of claim 17, further comprising:

removing material from a second surface of the substrate opposite the first surface, so that the conductive material extends from the first surface to the second surface of the substrate, to form a conductive through-substrate-via (TSV)

20. The method of claim 19, further comprising:

a) forming an oxide layer on the first surface of the substrate;

b) forming an etch stop layer on the oxide layer formed on the first surface of the substrate;

c) etching a portion of the etch stop layer using anisotropic etching; and

d) etching a portion of the oxide layer formed on the first surface of the substrate using anisotropic etching;

wherein the dielectric layer is formed on the etch stop layer and between the implanted side wall in the opening and the conductive material of the TSV.