METHOD, SYSTEM AND MEDIUM FOR ANALOG ENCRYPTION IN A FLASH MEMORY

• US 20110302428A1
• Filed: 04/06/2011
• Published: 12/08/2011
• Est. Priority Date: 04/06/2010
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Inventors: WEINGARTEN, Hanan
• Granted Patent: US 9,104,610 B2
• Time in Patent Office: Days
• US Class Current: 713/193
• CPC Class Codes: G06F 12/1408 by using cryptography for digital transmission H04L9/00
• CPC Class Codes: G06F 21/79 in semiconductor storage media, e.g. directly-addressable memories
• CPC Class Codes: G06F 2221/2107 File encryption
• CPC Class Codes: G09C 1/00 Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system cryptographic typewriters G09C3/00
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: H04L 9/065 Encryption by serially and continuously modifying data stream elements, e.g. stream cipher systems, RC4, SEAL or A5/3
• CPC Class Codes: H04L 9/14 using a plurality of keys or algorithms

Abstract

A system and method for analog encryption and decryption, in which the encryption and encoding processes are interrelated, such that by failing to decrypt the retrieved data, decryption fails.

Claims

1. A method performed by a memory controller comprising:

encrypting input data using a base key and an auxiliary key, wherein decryption of the encrypted input data requires the auxiliary key, and wherein the auxiliary key is only recoverable based on obtaining encrypted input data containing no errors; and

causing the encoded input data to be stored in a memory.

2. The method of claim 1, wherein encrypting input data comprises:

generating cipher data by performing a logical exclusive OR (XOR) operation on a key stream and an input data stream, wherein the key stream is dependent on a first encoding function;

generating intermediate encoded cipher data based on a second encoding function performed on the cipher data; and

generating final encoded cipher data based on the intermediate encoded cipher data and a result of the first encoding function.

3. The method of claim 2, further comprising generating the key stream by:

performing the first encoding function on the base key to generate a codeword;

using the codeword to generate the auxiliary key and syndrome values;

performing a logical exclusive OR (XOR) operation on the auxiliary key and a cipher key to obtain a combined key; and

using the combined key to generate the key stream.

4. The method of claim 3, wherein the auxiliary key is obtained from a syndrome calculation of the entire codeword.

5. The method of claim 1, wherein the memory is a Flash memory.

6. The method of claim 5, further comprising prior to causing the encoded input data to be stored in the flash memory, cycling the block containing the page such that following retention a sufficient number of errors occur to prohibit decoding.

7. The method of claim 5, further comprising prior to causing the encoded input data to be stored in the flash memory, modifying programming thresholds and incremental stepped pulse programming (ISPP) parameters of the Flash memory to increase the number of errors due to retention.

8. A memory controller configured to:

encrypt input data using a base key and an auxiliary key, wherein decryption of the encrypted input data requires the auxiliary key, and wherein the auxiliary key is only recoverable based on obtaining encrypted input data containing no errors; and

cause the encoded input data to be stored in a memory.

9. The memory controller of claim 8, wherein the memory controller is configured to encrypt input data by:

generating cipher data by performing a logical exclusive OR (XOR) operation on a key stream and an input data stream, wherein the key stream is dependent on a first encoding function;

generating intermediate encoded cipher data based on a second encoding function performed on the cipher data; and

generating final encoded cipher data based on the intermediate encoded cipher data and a result of the first encoding function.

10. The memory controller of claim 9, wherein the memory controller is configured to generate the key stream by:

performing the first encoding function on the base key to generate a codeword;

using the codeword to generate the auxiliary key and syndrome values;

performing a logical exclusive OR (XOR) operation on the auxiliary key and a cipher key to obtain a combined key; and

using the combined key to generate the key stream.

11. The memory controller of claim 10, wherein the memory controller is to obtain the auxiliary key from a syndrome calculation of the entire codeword.

12. The memory controller of claim 8, wherein the memory is a Flash memory.

13. The memory controller of claim 12, wherein prior to causing the encoded input data to be stored in the flash memory the memory controller is configured to cycle the block containing the page such that following retention a sufficient number of errors occur to prohibit decoding.

14. The memory controller of claim 12, wherein prior to causing the encoded input data to be stored in the flash memory the memory controller is configured to modify programming thresholds and incremental stepped pulse programming (ISPP) parameters of the Flash memory to increase the number of errors due to retention.