PASSIVE INTEGRATED CIRCUIT

• US 20110304014A1
• Filed: 06/08/2011
• Published: 12/15/2011
• Est. Priority Date: 06/10/2010
• Status: Active Grant

• Current Assignee: STMicroelectronics SAS (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SAS (STMicroelectronics NV)
• Inventors: Laporte, Claire, Ezzeddine, Hilal
• Granted Patent: US 9,117,693 B2
• Time in Patent Office: Days
• US Class Current: 257/531
• CPC Class Codes: H01L 2224/02166 Collar structures
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05666 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 27/016 Thin-film circuits
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00013 Fully indexed content
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/19011 : including integrated passive components
• CPC Class Codes: H03H 5/02 : without voltage- or current-dependent elements

Abstract

A passive integrated circuit formed on a substrate, including contact areas of a conductive material specifically capable of receiving bonding pads, wherein the conductive material further creates connections between regions of a lower metallization level.

Claims

1. A passive integrated circuit formed on a substrate, comprising contact areas of a conductive material specifically capable of receiving bonding pads, said conductive material comprising a stack of a titanium layer, a nickel layer, a copper layer, and a gold layer, wherein said conductive material further creates connections between regions of a lower metallization level.

2. The circuit of claim 1, comprising at least one inductance formed of a winding to made in said lower metallization level, wherein said conductive material creates a connection between the inner end of the winding and a component of the circuit.

3. The circuit of claim 2, wherein said component is a capacitor.

4. The circuit of claim 1, wherein said conductive material has a total thickness of approximately 1.5 μ

m.

5. The circuit of claim 1, wherein the lower metallization level is made of copper.

6. A method for manufacturing a passive integrated circuit, comprising the steps of:

forming, above a substrate, first conductive regions of a first metallization level; and

forming, above the first metallization level, second conductive regions of a conductive material specifically capable of receiving bonding pads, said conductive material comprising a stack of a titanium layer, a nickel layer, a copper layer, and a gold layer, these second conductive regions forming;

contact areas for ensuring connections to the outside; and

connections between first conductive regions.

7. The method of claim 6, wherein said circuit comprises at least one inductance formed of a winding made in the first metallization level, said conductive material creating a connection between the inner end of the winding and a component of the circuit.

8. The method of claim 7, wherein said component is a capacitor.

9. The method of claim 6, wherein the first metallization level is made of copper.

10. The method of claim 6, further comprising a preliminary step, at the design level, of decrease of the length of the connections between the first conductive regions.