VIRTUALIZED ECC NAND

• US 20110307762A1
• Filed: 10/09/2008
• Published: 12/15/2011
• Est. Priority Date: 10/09/2008
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Campardo, Giovanni, Vitale, Ornella, Pollio, Antonino, Tiziani, Federico, Iaculo, Massimo, Giaccio, Claudio, Scognamiglio, Manuela, Caraccio, Danilo
• Granted Patent: US 8,806,293 B2
• Time in Patent Office: Days
• US Class Current: 714/768
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: G06F 11/1044 with specific ECC/EDC distribution
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 13/1668 Details of memory controller
• CPC Class Codes: G06F 3/0625 Power saving in storage systems
• CPC Class Codes: G06F 3/0634 by changing the state or mode of one or more devices
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A single virtualized ECC NAND controller executes an ECC algorithm and manages a stack of NAND flash memories. The virtualized ECC NAND controller allows the host processor to drive the stack of flash memory devices as a single NAND chip while the controller redirects the data to the selected NAND memory device in the stack.

Claims

1. A storage system to couple to a host, comprising:

first and second NAND memory devices in the storage system; and

a controller external to the first and second NAND memory devices that exports to the host a virtualized address space to allow the host to drive the storage system as a single NAND chip even though the storage system includes multiple NAND memory devices.

2. The storage system of claim 1, wherein the controller implements an Error Correcting Code (ECC) algorithm and not data management algorithms of wear leveling and bad block management.

3. The storage system of claim 2, wherein the controller includes a protocol interface circuit with a buffer to reduce latency introduced by calculations of the ECC algorithm.

4. The storage system of claim 3, wherein the protocol interface circuit manages a NAND Ready/Busy signal to the host processor to account for ECC algorithm latency.

5. The storage system of claim 1, wherein the controller manages a page size of the first NAND memory device that is different from the page size of the host.

6. The storage system of claim 1, wherein the controller adapts commands issued by the host that are not supported by the first and second NAND memory devices.

7. The storage system of claim 1, wherein the controller is a non-volatile memory device that redirects data received from the host processor to a selected NAND memory device.

8. A controller to interface with NAND memory in a storage system, comprising:

a protocol interface circuit to exchange signals with a host processor;

an ECC engine to implement an ECC algorithm; and

a NAND interface to manage the NAND memory, wherein commands issued by the host processor that are not supported by NAND memory are emulated in the controller.

9. The controller of claim 8, wherein the controller is a bridge from a host NAND interface to the NAND memory that selects an ECC algorithm to the host processor for the NAND memory provided in the storage system.

10. The controller of claim 8, wherein the controller manages a page size from the host processor that is different from the page size of the NAND memory.

11. The controller of claim 8, wherein the controller presents a single NAND interface to the host processor that removes a restriction on a number of usable flashes in the NAND memory due to available address input cycles.

12. The controller of claim 8, wherein the controller includes a protocol interface circuit with a buffer to transfer data to the host processor having buffering capabilities to read a second page of data for parallelizing ECC algorithm execution in a sequential read operation.

13. The controller of claim 12, wherein the protocol interface circuit manages a NAND Ready/Busy signal to the host processor to account for ECC algorithm latency.

14. A method of managing a stack of NAND memory devices that do not internally implement an ECC algorithm, comprising:

using a protocol interface block of a controller device to exchange signals with a host processor that allows the host processor to communicate with a large error free address space;

implementing an ECC algorithm by an ECC engine block embedded in the controller device; and

re-elaborating both commands and addresses received from the host processor by a NAND interface block embedded in the controller device to manage data transfers to the stack of NAND memory devices.

15. The method of claim 14, further including:

interpreting commands received from the host processor by the protocol interface block to direct the storage of data from the host processor.

16. The method of claim 14, further including:

loading a buffer in the protocol interface block having buffering capabilities to read a second page of data for parallelizing ECC algorithm execution in a sequential read operation.

17. A wireless communication system including multiple NAND memory devices, comprising:

a transceiver;

a processor having first and second processor cores, wherein the processor is coupled to the transceiver; and

an ECC controller having an embedded NAND interface block to receive commands and addresses and exchange signals with the processor, an ECC engine to implement an ECC algorithm, and a NAND interface circuit to re-elaborate both commands and addresses received from the host processor to direct data transfers with the multiple NAND memory devices.

18. The wireless communication system of claim 17 wherein the ECC controller further includes a protocol interface circuit having a buffer to reduce latency introduced by calculations of the ECC algorithm.

19. The wireless communication system of claim 17 wherein the ECC controller allows the processor to drive the multiple NAND memory devices as a single NAND chip while the ECC controller redirects data received from the processor to a selected NAND memory device.

20. The wireless communication system of claim 17 wherein the ECC controller allows the processor to manage a page size that differs from a page size of the multiple NAND memory devices.