VIRTUALIZED ECC NAND
First Claim
Patent Images
1. A storage system to couple to a host, comprising:
- first and second NAND memory devices in the storage system; and
a controller external to the first and second NAND memory devices that exports to the host a virtualized address space to allow the host to drive the storage system as a single NAND chip even though the storage system includes multiple NAND memory devices.
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Abstract
A single virtualized ECC NAND controller executes an ECC algorithm and manages a stack of NAND flash memories. The virtualized ECC NAND controller allows the host processor to drive the stack of flash memory devices as a single NAND chip while the controller redirects the data to the selected NAND memory device in the stack.
32 Citations
20 Claims
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1. A storage system to couple to a host, comprising:
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first and second NAND memory devices in the storage system; and a controller external to the first and second NAND memory devices that exports to the host a virtualized address space to allow the host to drive the storage system as a single NAND chip even though the storage system includes multiple NAND memory devices. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A controller to interface with NAND memory in a storage system, comprising:
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a protocol interface circuit to exchange signals with a host processor; an ECC engine to implement an ECC algorithm; and a NAND interface to manage the NAND memory, wherein commands issued by the host processor that are not supported by NAND memory are emulated in the controller. - View Dependent Claims (9, 10, 11, 12, 13)
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14. A method of managing a stack of NAND memory devices that do not internally implement an ECC algorithm, comprising:
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using a protocol interface block of a controller device to exchange signals with a host processor that allows the host processor to communicate with a large error free address space; implementing an ECC algorithm by an ECC engine block embedded in the controller device; and re-elaborating both commands and addresses received from the host processor by a NAND interface block embedded in the controller device to manage data transfers to the stack of NAND memory devices. - View Dependent Claims (15, 16)
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17. A wireless communication system including multiple NAND memory devices, comprising:
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a transceiver; a processor having first and second processor cores, wherein the processor is coupled to the transceiver; and an ECC controller having an embedded NAND interface block to receive commands and addresses and exchange signals with the processor, an ECC engine to implement an ECC algorithm, and a NAND interface circuit to re-elaborate both commands and addresses received from the host processor to direct data transfers with the multiple NAND memory devices. - View Dependent Claims (18, 19, 20)
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Specification