Semiconductor device and method for manufacturing the same

• US 20110309353A1
• Filed: 05/27/2011
• Published: 12/22/2011
• Est. Priority Date: 06/22/2010
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Kaneko, Kishou, Inoue, Naoya, Hayashi, Yoshihiro
• Granted Patent: US 8,618,537 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/458 for thin film silicon, e.g. source or drain electrode
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A semiconductor device includes, in a first region over a semiconductor substrate, a first insulating layer, a first wiring, a second insulating layer, a third insulating layer, and a via and a second wiring embedded in the second insulating layer and the third insulating layer through a barrier metal, and includes, in a second region, the first insulating layer, a gate electrode, the second insulating layer, a semiconductor layer located, the third insulating layer, and a first electric conductor and a second electric conductor embedded in the third insulating layer so as to sandwich the gate electrode in a position overlapped with the semiconductor layer in a plan view through a barrier metal and coupled to the semiconductor layer through the barrier metal.

Claims

1. A semiconductor device comprising, in a first region over a semiconductor substrate:

a first insulating layer located over the semiconductor substrate;

a first wiring embedded into the surface of the first insulating layer;

a second insulating layer located over the first insulating layer;

a third insulating layer located over the second insulating layer; and

a via and a second wiring embedded into the second insulating layer and the third insulating layer through a barrier metal and coupled to the first wiring, and

further comprising, in a second region over the semiconductor substrate;

the first insulating layer located over the semiconductor substrate;

a gate electrode embedded into the surface of the first insulating layer;

the second insulating layer located over the first insulating layer;

a semiconductor layer located over the second insulating layer;

the third insulating layer located over the semiconductor layer; and

a first electric conductor and a second electric conductor embedded into the third insulating layer so as to sandwich the gate electrode in a position overlapped with the semiconductor layer in a plan view through a barrier metal and coupled to the semiconductor layer through the barrier metal.

2. The semiconductor device according to claim 1,

wherein at least one of a first contact region of the barrier metal contacting to the first electric conductor and the semiconductor layer and a second contact region of the barrier metal contacting to the second electric conductor and the semiconductor layer is not overlapped with the gate electrode in a plan view.

3. The semiconductor device according to claim 2,

wherein one of the first contact region and the second contact region is overlapped with the gate electrode in a plan view and the other is not overlapped with the gate electrode in a plan view.

4. The semiconductor device according to claim 1,

wherein the device comprises a plurality of the second regions;

wherein at least one of a first contact region of the barrier metal contacting to the first electric conductor and the semiconductor layer and a second contact region of the barrier metal contacting to the second electric conductor and the semiconductor layer are not overlapped with the gate electrode in a plan view in a primary second region; and

wherein both of the first contact region and the second contact region are overlapped with the gate electrode in a plan view in a secondary second region.

5. The semiconductor device according to any one of claims 1 to 4,

wherein the semiconductor layer is an InGaZnO layer, an InZnO layer, a ZnO layer, ZnAlO layer or a ZnCuO layer.

6. The semiconductor device according to claim 1,

wherein a hard mask comprising one or more of SiN, SiO₂ and SiCOH is formed over the semiconductor layer;

and

wherein the first electric conductor and the second electric conductor embedded through the barrier metal penetrates the hard mask.

7. The semiconductor device according to claim 6,

wherein the hard mask stacks tow or more layers of a layer comprising SiN, a layer comprising SiO₂, and a layer comprising SiCOH.

8. The semiconductor device according to claim 6,

wherein the hard mask and the semiconductor layer have approximately the same planar shape.

9. The semiconductor device according to claim 1,

wherein the barrier metal comprises one or more elements selected from a first group consisting of Ti, Ta, Ru and W.

10. The semiconductor device according to claim 1,

wherein the via, the second wiring, the first electric conductor and the second electric conductor are comprised of the same material.

11. The semiconductor device according to claim 10,

wherein the via, the second wiring, the first electric conductor and the second electric conductor comprise Cu;

and

wherein the barrier metal comprises one or more elements selected from the first group consisting of Ti, Ta, Ru and W.

12. The semiconductor device according to claim 10,

wherein the via, the second wiring, the first electric conductor and the second electric conductor comprise Al;

and

wherein the barrier metal comprises one or more elements selected from the first group consisting of Ti, Ta, Ru and W.

13. The semiconductor device according to claim 1,

wherein the gate electrode is embedded into the first insulating layer with contacting to the second insulating layer;

and

wherein the first wiring and the gate electrode are comprised of the same material.

14. The semiconductor device according to claim 13,

wherein the first wiring and the gate electrode comprise Cu.

15. The semiconductor device according to claim 1, further comprising:

an on-substrate element including an on-substrate gate electrode formed over the semiconductor substrate through a gate insulating film; and

a source and a drain formed by doping impurity into the semiconductor substrate; and

wherein a wiring layer element including the gate electrode, the second insulating layer, the semiconductor layer, the barrier metal, the first electric conductor and the second electric conductor formed in the second region, and the on-substrate element are electrically coupled.

16. The semiconductor device according to claim 15,

wherein the first wiring layer element has a function which acts as switching operation caused by a first signal inputted from the on-substrate element electrically coupled to the gate electrode of the first wiring layer element to the aforementioned gate electrode, and supplies higher voltage to a first device coupled to the first wiring layer element than the voltage of the first signal by the aforementioned switching operation.

17. The semiconductor device according to claim 16,

wherein the first electric conductor of the first wiring layer element is electrically coupled to a first voltage power source which supplies higher voltage than the voltage of the first signal;

and

wherein the second electric conductor of the first wiring element is electrically coupled to the first device.

18. The semiconductor device according to claim 15,

wherein the second wiring layer element has a function which acts as switching operation caused by a second signal inputted from a second device electrically coupled to the gate electrode of the second wiring layer element to the aforementioned gate electrode, and supplies lower voltage to the on-substrate element than the voltage of the second signal by the aforementioned switching operation.

19. The semiconductor device according to claim 18,

wherein a first electric conductor of the second wiring layer element is electrically coupled to a second voltage power source which supplies lower voltage than the voltage of the second signal;

and

wherein the second electric conductor of the second wiring layer element is electrically coupled to the on-substrate element.

20. The semiconductor device according to claim 17,

wherein the first contact region of the barrier metal contacted to the first electric conductor and the semiconductor layer are not overlapped with the gate electrode in a plan view.

21. The semiconductor device according to claim 20,

wherein a second contact region of the barrier metal contacted to the second electric conductor and the semiconductor layer are overlapped with the gate electrode in a plan view.

22. A method for manufacturing a semiconductor device, comprising the steps of:

forming a first insulating layer over a semiconductor substrate;

embedding a conductive material into the first insulating layer to form a first wiring and a gate electrode;

forming a second insulating layer over the first insulating layer after the step above;

selectively forming a semiconductor layer in a region overlapped with the gate electrode in a plan view over the second insulating layer;

forming a third insulating layer over the semiconductor layer and the second insulating layer;

embedding a conductive material into the third insulating layer through a barrier metal so as to sandwich the gate electrode in a position overlapped with the semiconductor layer in a plan view to form a first electric conductor and a second electric conductor coupled to the semiconductor layer through the barrier metal, and at the same time, embedding a conductive material into the second insulating layer and the third insulating layer through a barrier metal to form a via and a second wiring coupled to the first wiring through the barrier metal.

23. The method for manufacturing the semiconductor device according to claim 22,

wherein, in the step of embedding a conductive material into the third insulating layer, in a state after embedding, at least one of a first contact region of the barrier metal contacted to the first electric conductor and the semiconductor layer, and a second contact region of the barrier metal contacted to the second electric conductor and the semiconductor layer are not overlapped with the gate electrode in a plan view.

24. The method for manufacturing the semiconductor device according to claim 23,

wherein, in the step of embedding a conductive material into the third insulating layer, in a state after embedding, one of the first contact region and the second contact region is overlapped with the gate electrode and the other is not overlapped with the gate electrode in a plan view.

25. The method for manufacturing the semiconductor device according to claim 22,

wherein, in the step of embedding a conductive material into the first insulating layer, a first gate electrode and a second gate electrode are formed;

wherein, in the step of embedding a conductive material into the third insulating layer, in a state after embedding, at least one of the first contact region and the second contact region of each of the barrier metal contacting to each of the first electric conductor and the second electric conductor sandwiching the first gate electrode and the semiconductor layer is not overlapped with the first gate electrode in a plan view; and

wherein both of the first contact region and the second contact region of each of the barrier metal contacting to each of the first electric conductor and the second electric conductor sandwiching the second gate electrode and the semiconductor layer are overlapped with the second gate electrode in a plan view.

26. The method for manufacturing the semiconductor device according to claim 22,

wherein the step of embedding a conductive material into the third insulating layer includes:

forming a connection hole in which the semiconductor layer is exposed to the third insulating layer;

treating the semiconductor layer exposing at the bottom surface of the connection hole by reduction plasma or nitrogen-containing plasma; and

embedding a conductive material into the connection hole through a barrier metal after the step above.

27. The method for manufacturing the semiconductor device according to claim 22,

wherein the step of selectively forming a semiconductor layer includes:

forming a semiconductor layer over the second insulating layer;

selectively forming a hard mask comprising one or more of SiN, SiO₂ and SiCOH in a region overlapped with the gate electrode in a plan view over the semiconductor layer; and

performing dry etching of the semiconductor layer using the hard mask as a mask, and

wherein the step of embedding a conductive material into the third insulating layer includes;

embedding a conductive material into the third insulating layer and the hard mask through a barrier metal so as to sandwich the gate electrode in a position overlapped with the semiconductor layer in a plan view to from the first electric conductor and the second electric conductor coupled to the semiconductor layer through a barrier metal, and at the same time, embedding a conductive material into the third insulating layer and the second insulating layer through a barrier metal to from the via and the second wiring coupled to the first wiring through the barrier metal.

33. The method for manufacturing the semiconductor device according to claim 27,

wherein the step of embedding a conductive material into the third insulating layer step includes:

forming a connection hole in which the semiconductor layer is exposed to the third insulating layer and the hard mask;

treating the semiconductor layer exposing at the bottom surface of the connection hole by reduction plasma or nitrogen-containing plasma; and

embedding a conductive material into the connection hole through a barrier metal after the step above.

34. The method for manufacturing the semiconductor device according to claim 27,

wherein oxidation treatment is performed to the semiconductor layer after the step of forming a semiconductor layer and before the step selectively forming a hard mask.

35. The method for manufacturing the semiconductor device according to claim 34,

wherein the oxidation treatment is plasma treatment using O₂ or N₂O.

36. The method for manufacturing the semiconductor device according to claim 27,

wherein the hard mask stacks tow or more layers of a layer comprising SiN, a layer comprising SiO₂, and a layer comprising SiCOH.

37. The method for manufacturing the semiconductor device according to claim 22,

wherein the semiconductor layer is an InGaZnO layer, an InZnO layer, a ZnO layer, ZnAlO layer or a ZnCuO layer.

38. The method for manufacturing the semiconductor device according to claim 22,

wherein the semiconductor layer is an oxide semiconductor layer and, in the step for forming the semiconductor layer, the semiconductor substrate is heated at a temperature of 400°

C. or lower.

28. A method for manufacturing a semiconductor device comprising the steps of:

forming a first insulating layer over a semiconductor substrate;

embedding a conductive material into the first insulating layer to form a first wiring and a gate electrode;

forming a second insulating layer over the first insulating layer after the step above;

forming a semiconductor layer over the second insulating layer;

selectively forming a hard mask comprising one or more of SiN, SiO₂ and SiCOH in a region overlapped with the gate electrode in a plan view over the semiconductor layer; and

performing dry etching of the semiconductor layer using the hard mask as a mask.

29. The method for manufacturing the semiconductor device according to claim 28, further comprising:

forming a third insulating layer over the hard mask and the second insulating layer after the step of performing dry etching; and

embedding a conductive material into the third insulating layer and the hard mask through a barrier metal so as to sandwich the gate electrode in a position overlapped with the semiconductor layer in a plan view to from the first electric conductor and the second electric conductor coupled to the semiconductor layer through the barrier metal, and, at the same time, embedding a conductive material into the third insulating layer and the second insulating layer through a barrier metal to from a via and a second wiring coupled to the first wiring through the barrier metal.

30. The method for manufacturing the semiconductor device according to claim 29,

wherein, in the step of embedding a conductive material into the third insulating layer, in a state after embedding, at least one of a first contact region of the barrier metal contacted to the first electric conductor and the semiconductor layer, and a second contact region of the barrier metal contacted to the second electric conductor and the semiconductor layer are not overlapped with the gate electrode in a plan view.

31. The method for manufacturing the semiconductor device according to claim 30,

wherein, in the step of embedding a conductive material into the third insulating layer, in a state after embedding, one of the first contact region and the second contact region is overlapped with the gate electrode and the other is not overlapped with the gate electrode in a plan view.

32. The method for manufacturing the semiconductor device according to claim 29,

wherein, in the step of embedding a conductive material into the first insulating layer, a first gate electrode and a second gate electrode are formed;

wherein, in the step of embedding a conductive material into the third insulating layer, in a state after embedding, at least one of the first contact region and the second contact region of each of the barrier metal contacting to each of the first electric conductor and the second electric conductor sandwiching the first gate electrode and the semiconductor layer is not overlapped with the first gate electrode in a plan view; and

wherein both of the first contact region and the second contact region of each of the barrier metal contacting to each of the first electric conductor and the second electric conductor sandwiching the second gate electrode and the semiconductor layer are overlapped with the second gate electrode in a plan view.