Simultaneously Tagging of Semiconductor Components on a Wafer

• US 20110309852A1
• Filed: 02/17/2011
• Published: 12/22/2011
• Est. Priority Date: 06/16/2010
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Behzad, Arya Reza, Rofougaran, Ahmadreza, Zhao, Sam Ziqun, Castaneda, Jesus Alfonso, Boers, Michael
• Granted Patent: US 8,866,502 B2
• Time in Patent Office: Days
• US Class Current: 324/750.15
• CPC Class Codes: G01R 31/2834 Automated test systems [ATE]; using microprocessors or computers G01R31/317 takes precedence; ATE for detection of defective computer hardware G06F11/2736
• CPC Class Codes: G01R 31/3025 Wireless interface with the DUT
• CPC Class Codes: G01R 31/311 of integrated circuits G01R31/31728 takes precedence
• CPC Class Codes: G01R 31/319 Tester hardware, i.e. output processing circuits
• CPC Class Codes: H01L 2223/54433 containing identification or tracking information
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10T 29/49121 Beam lead frame or beam lead device

Abstract

Methods and apparatus are disclosed to simultaneously, wirelessly test semiconductor components formed on a semiconductor wafer. The semiconductor components transmit respective outcomes of a self-contained testing operation to wireless automatic test equipment via a common communication channel. Multiple receiving antennas observe the outcomes from multiple directions in three dimensional space. The wireless automatic test equipment determines whether one or more of the semiconductor components operate as expected and, optionally, may use properties of the three dimensional space to determine a location of one or more of the semiconductor components. The wireless testing equipment may additionally determine performance of the semiconductor components by detecting infrared energy emitted, transmitted, and/or reflected by the semiconductor wafer before, during, and/or after a self-contained testing operation.

Claims

1. A wireless automatic test equipment for simultaneously testing a plurality of semiconductor components formed onto a semiconductor wafer, comprising:

a transmitter module configured to simultaneously send a plurality of initiate self-contained testing operation signals to the plurality of semiconductor components;

a receiver module configured to receive a plurality of testing operation outcomes from the plurality of semiconductor components over a common communication channel to provide a plurality of recovered testing outcomes, the plurality of testing outcomes indicating whether its respective semiconductor component operates as expected,

a testing processor configured to determine a first group of semiconductor components from among the plurality of semiconductor components that operate as expected based upon the plurality of recovered testing outcomes.

2. The wireless automatic test equipment of claim 1, further comprising:

a plurality of transmitting antennas, coupled to the transmitter module, configured to simultaneously send the initiate self-contained testing operation signal to the plurality of semiconductor components.

3. The wireless automatic test equipment of claim 2, wherein the plurality of transmitting antennas are positioned along a radius of a spherical shell in the three dimensional space.

4. The wireless automatic test equipment of claim 2, wherein the plurality of transmitting antennas are positioned along a corresponding radius from among a plurality of radii of a corresponding spherical shell from among a plurality of spherical shells in the three dimensional space.

5. The wireless automatic test equipment of claim 1, wherein the receiver module is further configured to simultaneously receive the plurality of testing operation outcomes over a common communication channel.

6. The wireless automatic test equipment of claim 1, wherein the receiver module is further configured to decode the plurality of testing operation outcomes in accordance with a multiple access transmission scheme to provide the plurality of recovered testing outcomes.

7. The wireless automatic test equipment of claim 6, wherein the multiple access transmission scheme is a code division multiple access (CDMA) scheme.

8. The wireless automatic test equipment of claim 1, wherein the testing processor is further configured to determine a second group of semiconductor components from among the plurality of semiconductor components that operate unexpectedly based upon the plurality of recovered testing outcomes.

9. The wireless automatic test equipment of claim 1, wherein each of the plurality of testing operation outcomes is characterized as having a unique identification number from among a plurality of unique identification numbers that identifies one of the plurality of semiconductor components.

10. The wireless automatic test equipment of claim 9, wherein the testing processor is configured to determine a location of the plurality of semiconductor components based upon the plurality of unique identification numbers.

11. The wireless automatic test equipment of claim 10, wherein the testing processor is further configured to assemble a map indicating the location of the plurality of semiconductor components by comparing the plurality of unique identification numbers to a predetermined mapping of the plurality of unique identification numbers to their respective locations within the semiconductor wafer.

12. The wireless automatic test equipment of claim 10, wherein the testing processor is further configured to iteratively map the plurality of unique identification numbers to their corresponding semiconductor component based upon relationships between the plurality of unique identification numbers.

13. A semiconductor component formed on a semiconductor wafer, comprising:

a transceiver module configured to receive a plurality of initiate testing operation signals to provide a plurality of initiate test control signals;

a metric measurement module configured to determine a plurality of signal metrics for the a plurality of initiate test control signals;

a testing module configured to generate a unique identification number for the semiconductor component based upon the plurality of signal metrics and to provide a self-contained testing operation in response to the plurality of initiate test control signals;

an integrated circuit under test configured to provide an indication of operability in response to executing the self-contained testing operation, the indication of operability indicating whether the integrated circuit under test operates as expected,

wherein the testing module is further configured to append the unique identification number to the indication of operability.

14. The semiconductor component of claim 13, wherein the transceiver module is configured to encode the indication of operability in accordance with a multiple access transmission scheme.

15. The semiconductor component of claim 14, wherein the multiple access transmission scheme is a code division multiple access (CDMA) scheme.

16. The semiconductor component of claim 13, wherein the plurality of initiate testing operation signals causes the testing module to enter into a testing mode of operation whereby the testing module provides the self-contained testing operation to the integrated circuit under test.

17. The semiconductor component of claim 13, wherein the transceiver module comprises:

a downconverter module configured to downconvert the plurality of initiate test control signals to provide a plurality of downconverted testing operation outcomes;

a demodulating module configured to demodulate the plurality of downconverted testing operation outcomes in accordance with a digital modulation technique to provide a plurality of demodulated testing operation outcomes; and

a decoding module configured to decode the plurality of demodulated testing operation outcomes in accordance with a multiple access transmission scheme to provide the plurality of initiate test control signals.

18. A semiconductor component formed on a semiconductor wafer, comprising:

a transceiver module configured to receive a plurality of initiate testing operation signals to provide a plurality of initiate test control signals;

a testing module configured to generate a unique identification number for the semiconductor component and to provide a self-contained testing operation in response to the plurality of initiate test control signals;

an integrated circuit under test configured to provide an indication of operability in response to executing the self-contained testing operation, the indication of operability indicating whether the integrated circuit under test operates as expected,

wherein the testing module is further configured to append the unique identification number to the indication of operability.

19. The semiconductor component of claim 18, wherein the transceiver module is configured to encode the indication of operability in accordance with a multiple access transmission scheme.

20. The semiconductor component of claim 19, wherein the multiple access transmission scheme is a code division multiple access (CDMA) scheme.

21. The semiconductor component of claim 18, wherein the plurality of initiate testing operation signals causes the testing module to enter into a testing mode of operation whereby the testing module provides the self-contained testing operation to the integrated circuit under test.

22. The semiconductor component of claim 18, wherein the transceiver module comprises:

a downconverter module configured to downconvert the plurality of initiate test control signals to provide a plurality of downconverted testing operation outcomes;

a demodulating module configured to demodulate the plurality of downconverted testing operation outcomes in accordance with a digital modulation technique to provide a plurality of demodulated testing operation outcomes; and

a decoding module configured to decode the plurality of demodulated testing operation outcomes in accordance with a multiple access transmission scheme to provide the plurality of initiate test control signals.

23. The semiconductor component of claim 18, wherein the testing module comprises:

a random number generator configured to generate the unique identification number.