SYSTEMS AND METHODS FOR SUBDIVIDING AND STORING VERTEX DATA

• US 20110310102A1
• Filed: 06/17/2010
• Published: 12/22/2011
• Est. Priority Date: 06/17/2010
• Status: Abandoned Application

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Chang, Hua-Yu
• Application Number:
  US12/817,294
• Publication Number:
  US 20110310102A1
• Time in Patent Office: Days
• US Class Current: 345/423
• CPC Class Codes: G06T 17/20 Finite element generation, e.g. wire-frame surface description, tesselation

Abstract

Systems and methods for subdividing patches and storing control points are described. At least one embodiment is a method for storing vertex data in a graphics processor. The method comprises receiving a patch to be tessellated, subdividing the patch into a plurality of triangles, and identifying control points of each of the plurality of triangles. The method further comprises assigning an identifier to each of the vertices, and selectively storing only a portion of the vertices in a memory.

Claims

1. A method for storing vertex data in a graphics processor, comprising:

receiving a patch to be tessellated;

subdividing the patch into a plurality of triangles;

identifying vertices of each of the plurality of triangles;

assigning an identifier to each of the vertices; and

selectively storing only a portion of the vertices and their corresponding identifiers in a memory.

2. The method of claim 1, wherein subdividing the patch comprises:

forming an exterior ring of triangles comprising a plurality of exterior edges; and

forming an interior ring of triangles comprising a plurality of interior edges.

3. The method of claim 2, wherein vertices on the exterior ring of triangles are equally distributed about a halfway point on the exterior edges such that vertices mirror each other about an axis through the halfway point.

4. The method of claim 2, wherein vertices on the interior ring of triangles are equally distributed about a halfway point on the interior edges such that vertices mirror each other about an axis through the halfway point, and wherein distribution of the vertices among each of the interior edges is constant.

5. The method of claim 3, wherein selectively storing only a portion of the vertices in a memory comprises:

for each exterior edge, storing one half of the vertices on each exterior edge.

6. The method of claim 3, wherein selectively storing only a portion of the vertices in a memory comprises:

for a vertical interior edge and a horizontal interior edge, storing one half of the vertices on the vertical and horizontal interior edges.

7. The method of claim 2, wherein vertices on the interior ring of triangles are equally distributed about a halfway point on the interior edges, and wherein the distribution of the vertices is the same on each of the interior edges.

8. The method of claim 2, wherein assigning an identifier to each of the vertices is performed starting with a bottom left vertex on the exterior ring of the patch and assigning an identifier to each of the vertices in a spiraling, clock-wise fashion.

9. The method of claim 8, wherein assigning an identifier comprises assigning an integer identifier to each of the vertices in a sequential order.

10. The method of claim 1, wherein the memory comprises a vertex buffer.

11. A graphics processing unit (GPU) having a tessellator in a graphics pipeline configured to subdivide and store a patch, comprising:

triangulation logic configured to receive tessellation factors from a hull shader within the graphics pipeline, wherein the triangulation logic is further configured to subdivide the patch into triangles primitives defined by a plurality of vertices according to the tessellation factors;

vertex generation logic configured to assign vertex identifiers to each of the vertices of the triangle primitives generated by the triangulation logic; and

a topology module configured to derive topological information associated with the patch and forward the information to a primitive assembly block.

12. The GPU of claim 11, wherein triangulation logic is further configured to form an exterior ring of triangles comprising a plurality of exterior edges and an interior ring of triangles comprising a plurality of interior edges.

13. The GPU of claim 12, wherein vertices on the exterior edges of the exterior ring are equally distributed about an axis halfway on each of the exterior edges, wherein vertices on the interior edges of the interior ring are equally distributed about an axis halfway on each of the interior edges, and wherein the distribution of vertices is the same on each of the interior edges.

14. The GPU of claim 12, wherein the vertex generation logic is configured to assign vertex identifiers in a spiraling, clock-wise direction beginning with a bottom left vertex on the exterior ring, wherein assigning vertex identifiers comprises assigning an integer identifier to each of the vertices in a sequential order.

15. The GPU of claim 14, wherein the topology module is further configured to save, for each exterior edge, the vertices on one side of the axis located halfway on each of the exterior edges to a vertex buffer, and wherein the topology module is further configured to save, for a horizontal interior edge and a vertical interior edge, the vertices on one side of the axes located halfway on the interior edges to a vertex buffer.

16. The GPU of claim 15, wherein the topology module is further configured to save the identifiers assigned to the saved vertices.

17. A tessellator in a graphics processing unit (GPU), comprising:

logic configured to receive tessellation factors from a hull shader, wherein the logic is further configured to subdivide a patch into triangles defined by a plurality of vertices according to the tessellation factors, wherein the patch comprises one of;

a quad and a triangle;

logic configured to assign an index to each of the vertices; and

logic configured to store only a portion of the vertices in a vertex buffer based on symmetric attributes of the subdivided patch.

18. The tessellator of claim 17, wherein the logic configured to subdivide a patch is further configured to partition the subdivided patch into an exterior ring of triangles and an interior ring of triangles, wherein edges of the interior ring comprise equally distributed vertices such that the distribution of vertices on all the edges of the interior ring is the same.

19. The tessellator of claim 18, wherein the logic configured to assign an index to each of the vertices is further configured to assign integer indices in a spiraling, clock-wise direction beginning with a bottom left vertex on the exterior ring, wherein assigning integer indices is performed in a sequential order.

20. The tessellator of claim 18, wherein the logic configured to store a portion of the vertices in a vertex buffer stores:

for each exterior edge, the vertices on one side of the axis located halfway on each of the exterior edges, and

for a vertical interior edge and a horizontal interior edge, the vertices on one side of the axes located halfway on the interior edges to a vertex buffer,

wherein the logic configured to store a portion of the vertices in a vertex buffer is further configured to store the indices assigned to the stored vertices.