NON-VOLATILE MEMORY CONTROL

• US 20110310683A1
• Filed: 05/16/2011
• Published: 12/22/2011
• Est. Priority Date: 09/28/2001
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Gorobets, Sergey Anatolievich
• Granted Patent: US 8,208,322 B2
• Time in Patent Office: Days
• US Class Current: 365/194
• CPC Class Codes: G06F 13/1615 using a concurrent pipeline structrure
• CPC Class Codes: G06F 13/4239 with asynchronous protocol
• CPC Class Codes: G06F 3/0625 Power saving in storage systems
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Methods and apparatus for use in a memory system having a non-volatile memory and a controller for limiting the number of non-volatile memory arrays from a plurality of available arrays accessed at one time are useful in the control of concurrent access of memory arrays. One method includes implementing a pipelining sequence for transferring data to and from the non-volatile memory arrays and limiting the number of active arrays operating at one time. The controller is configured to wait for the at least one of the arrays to complete before initiating a transfer to and from a further array.

Claims

1. (canceled)

2. A method of operating a memory system, comprising:

initiating an operation for access of two or more groups of memory cells;

checking a current status of each of the two or more groups of memory cells during the operation;

determining a number of the two or more groups of memory cells that are simultaneously active during the operation;

delaying the operation if the number of the two or more groups of memory cells that are simultaneously active during the operation is at a particular value; and

continuing with the operation if the number of the two or more groups of memory cells that are simultaneously active during the operation is below the particular value.

3. The method of claim 2, further comprising:

initiating a second operation for access of the two or more groups of memory cells;

checking a current status of each of the two or more groups of memory cells during the second operation;

determining a number of the two or more groups of memory cells that are simultaneously active during the second operation;

delaying the operation if the number of the two or more groups of memory cells that are simultaneously active during the second operation is at a second particular value; and

continuing with the second operation if the number of the two or more groups of memory cells that are simultaneously active during the second operation is below the second particular value;

wherein the second operation is different than the operation;

wherein the second particular value is different than the particular value; and

wherein the operation and the second operation are selected from the group consisting of a read operation, a transfer operation, a programming operation, and an erase operation.

4. The method of claim 2, further comprising delaying the operation even though the memory system is capable of concurrent access of a number of groups of memory cells in excess of the particular value.

5. The method of claim 2, wherein initiating an operation for access of two or more groups of memory cells comprises initiating an operation for access of two or more memory arrays.

6. The method of claim 2, wherein initiating an operation for access of two or more groups of memory cells comprises initiating an operation for access of two or more memory chips.

7. The method of claim 2, wherein continuing with the operation if the number of the two or more groups of memory cells that are simultaneously active during the operation is below the particular value comprises accessing a next group of memory cells while accessing a previous group of memory cells.

8. The method of claim 2, further comprising:

adjusting the particular value in response to electrical parameters for the operation.

9. The method of claim 8, wherein adjusting the particular value in response to electrical parameters for the operation comprises adjusting the particular value to maintain an electrical current level of the memory system below a particular value during the operation.

10. The method of claim 8, wherein adjusting the particular value in response to electrical parameters for the operation comprises adjusting the particular value to maintain a particular ratio between performance and power consumption.

11. The method of claim 2, wherein initiating an operation for access of two or more groups of memory cells comprises initiating an operation for access of two or more groups of memory cells wherein only one access can be performed at any one time in each of the two or more groups of memory cells.

12. A method of operating a memory system, comprising:

initiating a sequential access of two or more groups of memory cells;

determining an electrical current level of the accessed groups of memory cells;

delaying access of one of the groups of memory cells if a next access in the sequence would exceed a particular value of the electrical current level; and

continuing with the sequential access when the next access in the sequence would produce an electrical current level below the particular value.

13. The method of claim 12, wherein initiating a sequential access of two or more groups of memory cells comprises:

initiating transfer of first data for a first group of memory cells;

initiating programming of the first data to the first group of memory cells;

initiating transfer of second data for a second group of memory cells while programming the first data to the first group of memory cells; and

initiating programming of the second data to the second group of memory cells while programming the first data to the first group of memory cells.

14. The method of claim 13, wherein initiating a sequential access of two or more groups of memory cells further comprises:

initiating transfer of third data for a third group of memory cells while programming the first data to the first group of memory cells and while programming the second data to the second group of memory cells; and

initiating programming of the third data to the third group of memory cells while programming the first data to the first group of memory cells and while programming the second data to the second group of memory cells.

15. The method of claim 13, wherein initiating a sequential access of two or more groups of memory cells further comprises:

initiating transfer of third data for a third group of memory cells while programming the second data to the second group of memory cells and after completion of programming the first data to the first group of memory cells; and

initiating programming of the third data to the third group of memory cells while programming the second data to the second group of memory cells.

16. A method of operating a memory system, comprising:

initiating a sequential access of two or more groups of memory cells;

determining a number of the two or more groups of memory cells that are simultaneously active during the sequential access;

delaying access of a next group of memory cells in the sequence if the number of the two or more groups of memory cells that are simultaneously active during the sequential access is at a particular value; and

accessing the next group of memory cells in the sequence when the number of the two or more groups of memory cells that are simultaneously active during the sequential access is below the particular value.

17. The method of claim 16, wherein initiating a sequential access of two or more groups of memory cells comprises:

initiating transfer of first data for a first group of memory cells;

initiating programming of the first data to the first group of memory cells;

initiating transfer of second data for a second group of memory cells while programming the first data to the first group of memory cells; and

initiating programming of the second data to the second group of memory cells while programming the first data to the first group of memory cells.

18. The method of claim 17, wherein delaying access of a next group of memory cells in the sequence comprises:

delaying transfer of third data for a third group of memory cells until programming of the first data to the first group of memory cells is completed, if the particular value is two.

19. The method of claim 16, wherein accessing the next group of memory cells in the sequence when the number of the two or more groups of memory cells that are simultaneously active during the sequential access is below the particular value comprises accessing the next group of memory cells while continuing to access a previous group of memory cells.

20. The method of claim 16, further comprising delaying access of the next group of memory cells in the sequence even though the memory system is capable of accessing the next group of memory cells.

21. The method of claim 16, further comprising adjusting the particular value in response to a type of access being performed.