APPARATUS AND METHODS TO ACHIEVE A VARIABLE COLOR PIXEL BORDER ON A NEGATIVE MODE SCREEN WITH A PASSIVE MATRIX DRIVE

• US 20110316867A1
• Filed: 05/25/2010
• Published: 12/29/2011
• Est. Priority Date: 11/08/2000
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Palm, Inc. (TCL Technology Group Corp.)
• Inventors: Lum, David W., Chan, Yichang
• Granted Patent: US 8,237,718 B2
• Time in Patent Office: Days
• US Class Current: 345/549
• CPC Class Codes: G09G 2310/0232 Special driving of display border areas
• CPC Class Codes: G09G 2320/029 by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel
• CPC Class Codes: G09G 2320/0606 Manual adjustment
• CPC Class Codes: G09G 2320/066 for control of contrast
• CPC Class Codes: G09G 2340/145 related to small screens
• CPC Class Codes: G09G 2360/12 Frame memory handling
• CPC Class Codes: G09G 3/2074 using sub-pixels
• CPC Class Codes: G09G 3/3622 using a passive matrix G09G3/3674 - G09G3/3696 take precedence
• CPC Class Codes: G09G 5/026 Control of mixing and/or overlay of colours in general G09G5/022 and G09G5/024 take precedence
• CPC Class Codes: G09G 5/39 Control of the bit-mapped memory
• CPC Class Codes: G09G 5/40 characterised by the way in which both a pattern determined by character code and another pattern are displayed simultaneously, or either pattern is displayed selectively, e.g. with character code memory and APA, i.e. all-points-addressable, memory

Abstract

A display unit is constituted by a passive matrix of independently controllable pixels characterized by an active area of n rows and m columns of discrete pixels and a pixel border. The pixel border has a predetermined width, in one embodiment two pixels. The border pixel color state is controlled herein by the frame buffer memory. The pixel border color state is controlled to correspond to information contained in a frame buffer memory locus. This locus may be, in various embodiments herein, a single pixel, a row of pixels, or a number of rows of pixels of frame buffer memory. Each row of pixels may be equal to m and/or n. In one embodiment, the frame buffer controls the border pixels directly via a liquid crystal display controller and drivers, without a timing generation mechanism, such as a timing ASIC.

Claims

1. A display unit comprising:

a display matrix of independently controllable pixels comprising n rows and m columns of discrete pixels, said display matrix operable to generate an image in response to electronic signals driven from row and column drivers coupled thereto, said image representative of information stored in a frame buffer memory; and

a pixel border surrounding said display matrix and comprising a plurality of pixels which are controlled to a color state by one or more unmapped locations of said frame buffer memory.

2. A display unit as described in claim 1 wherein said color state of said pixel border is controlled to correspond to information within a locus of said frame buffer, said locus comprising one or more unmapped memory locations within said frame buffer memory.

3. A display unit as described in claim 2 wherein said locus of said frame buffer comprises a single pixel of memory within said frame buffer.

4. A display unit as described in claim 2 wherein said locus of said frame buffer comprises a row of pixels of memory within said frame buffer.

5. A display unit as described in claim 4 wherein said row of pixels of memory within said frame buffer comprises n pixels of memory within said frame buffer.

6. A display unit as described in claim 2 wherein said locus of said frame buffer comprises a plurality of rows of pixels of memory within said frame buffer.

7. A display unit as described in claim 6 wherein each said row of pixels of memory within said frame buffer comprises n pixels of memory within said frame buffer, each said row mapping to a corresponding portion of said plurality of pixels comprising said pixel border.

8. A display unit as described in claim 1 wherein said passive matrix is negative display mode liquid crystal display technology.

9. A display unit as described in claim 8 wherein said unmapped memory locations within said frame buffer memory controls said plurality of pixels comprising said pixel border directly via a liquid crystal display controller and drivers;

without a timing generation mechanism.

10. A display unit as described in claim 8 wherein said liquid crystal display technology is supertwisted nematic.

11. A display unit as described in claim 1 wherein said predetermined width is two pixels.

12. A display unit as described in claim 1 wherein said passive matrix comprises 160 rows and 160 columns of discrete pixels.

13. A portable electronic device comprising:

a processor coupled to a bus;

a memory unit coupled to said bus;

a user input device coupled to said bus; and

a display unit coupled to said bus and comprising;

a display matrix of independently controllable pixels comprising n rows and m columns of discrete pixels, said display matrix operable to generate an image in response to electronic signals driven from row and column drivers coupled thereto, said image representative of information stored in a frame buffer memory; and

a pixel border surrounding said display matrix and comprising a plurality of pixels which are controlled to a color state by one or more unmapped locations of said frame buffer memory.

14. A portable electronic device as described in claim 13 wherein said color state of said pixel border is controlled to correspond to information within a locus of said frame buffer, said locus comprising one or more unmapped memory locations within said frame buffer memory.

15. A portable electronic device as described in claim 14 wherein said locus of said frame buffer comprises a single pixel of memory within said frame buffer.

16. A portable electronic device as described in claim 14 wherein said locus of said frame buffer comprises a row of pixels of memory within said frame buffer.

17. A portable electronic device as described in claim 16 wherein said row of pixels of memory within said frame buffer comprises n pixels of memory within said frame buffer.

18. A portable electronic device as described in claim 14 wherein said locus of said frame buffer comprises a plurality of rows of pixels of memory within said frame buffer.

19. A portable electronic device as described in claim 18 wherein each said row of pixels of memory within said frame buffer comprises n pixels of memory within said frame buffer, each said row mapping to a corresponding portion of said plurality of pixels comprising said pixel border.

20. A portable electronic device as described in claim 13 wherein said passive matrix is negative display mode liquid crystal display technology.

21. A portable electronic device as described in claim 20 wherein said frame buffer controls said plurality of pixels comprising said pixel border directly via a liquid crystal display controller and drivers, without a timing generation mechanism.

22. A display unit as described in claim 20 wherein said liquid crystal display technology is supertwisted nematic.

23. A display unit as described in claim 13 wherein-said predetermined width is two pixels.

24. A display unit as described in claim 13 wherein said passive matrix comprises 160 rows and 160 columns of discrete pixels.

25. In an electronic system comprising a hardware application layer with a frame buffer memory, and a negative display mode liquid crystal display with a passive matrix drive comprising a liquid crystal display controller, drivers, and a liquid crystal display matrix with an active pixel area and a pixel border, a method of controlling the color of said pixel border comprising:

monitoring a locus within said frame buffer memory for information;

determining a color for said pixel border corresponding to said information;

generating a pixel border color signal corresponding to said color;

transferring said pixel border color signal to said liquid crystal display controller;

generating a pixel border color writing signal corresponding to said pixel border color signal; and

impelling said drivers to write a color to said pixel border accordingly.

26. The method as recited in claim 25 wherein said monitoring a locus within said frame buffer memory for information, said determining a color for said pixel border corresponding to said information, and said generating a pixel border color signal corresponding to said color is performed by said hardware abstraction layer.

27. The method as recited in claim 25 wherein said impelling said drivers to write a color to said pixel border accordingly does not involve a timing synchronization mechanism external from said hardware abstraction layer.