Method for power management of data buses in electronic devices

• US 20110320841A1
• Filed: 09/21/2010
• Published: 12/29/2011
• Est. Priority Date: 06/23/2010
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Sinha, Rajesh Kumar
• Granted Patent: US 8,966,302 B2
• Time in Patent Office: Days
• US Class Current: 713/323
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3253 Power saving in bus
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Provided are systems and methods for execution by a core of a peripheral component to provide power management for a data bus in a electronic device, suhc as a mobile electronic device. One method comprises determining whether a device in the peripheral component is inactive, transmitting a request for deactivation of at least one data channel to the device, receiving a command to deactivate the at least one data channel, determining whether any remaining devices in the peripheral component are active, and placing the peripheral component in a first low power mode wherein the core remains active in order to monitor a data bus clock.

Claims

1. A method for execution by a core of a peripheral component to provide power management for a data bus in an electronic device, the method comprising:

determining that a device in the peripheral component is inactive;

transmitting a request for deactivation of at least one data channel to the device;

receiving a command to deactivate the at least one data channel;

determining that all remaining devices in the peripheral component are inactive; and

placing the peripheral component in a first low power mode, wherein the core remains active in the first low power mode in order to monitor a data bus clock.

2. The method of claim 1, wherein the determining that the device is inactive comprises detecting an inactivity timeout for the at least one data channel.

3. The method of claim 1, wherein the determining that the device is inactive comprises direct notification from the device that the device is inactive.

4. The method of claim 1, further comprising:

waking up the peripheral component;

determining that a reason for waking up the peripheral component comprises receiving a command to activate another at least one data channel; and

restarting the method of claim 1.

5. The method of claim 1, further comprising:

waking up the peripheral component;

determining that a reason for waking up the peripheral component comprises a self wake up;

determining that the data bus clock is not paused after waking up the peripheral component; and

transmitting a request to activate another at least one data channel to the device.

6. The method of claim 1, further comprising:

waking up the peripheral component;

determining that a reason for waking up the peripheral component comprises a self wake up;

determining that the data bus clock is paused after waking up the peripheral component;

requesting that the data bus clock be resumed; and

transmitting a request to activate another at least one data channel to the device.

7. The method of claim 1, further comprising:

detecting that the data bus clock is paused; and

placing the core in a second low power mode, wherein the core does not remain active in the second low power mode so as to further reduce power consumption.

8. The method of claim 1, further comprising:

detecting that the data bus clock is paused;

placing the core in a second low power mode, wherein the core does not remain active in the second low power mode so as to further reduce power consumption.

waking up the peripheral component;

determining that a reason for waking up the peripheral component comprises the data bus clock was resumed; and

placing the peripheral component in a first low power mode, wherein the core remains active in the first low power mode in order to monitor a data bus clock.

9. The method of claim 1, further comprising:

detecting that the data bus clock is paused;

placing the core in a second low power mode, wherein the core does not remain active in the second low power mode so as to further reduce power consumption.

waking up the peripheral component;

determining that a reason for waking up the peripheral component comprises a self wake up;

determining that the data bus clock is not paused after waking up the peripheral component; and

transmitting a request to activate another at least one data channel to the device.

10. The method of claim 1, further comprising:

detecting that the data bus clock is paused;

placing the core in a second low power mode, wherein the core does not remain active in the second low power mode so as to further reduce power consumption.

waking up the peripheral component;

determining that a reason for waking up the peripheral component comprises a self wake up; and

determining that the data bus clock is paused after waking up the peripheral component;

requesting that the data bus clock be resumed; and

transmitting a request to activate another at least one data channel to the device.

11. A system for providing power management for a data bus in a electronic device, the system comprising:

at least one peripheral component having a core configured to;

determine that a device in the peripheral component is inactive;

transmit a request for deactivation of at least one data channel to the device;

receive a command to deactivate the at least one data channel;

determine that all remaining devices in the peripheral component are inactive; and

place the peripheral component in a first low power, wherein the core remains active in the first low power mode in order to monitor a data bus clock.

12. The system of claim 11, wherein the core is further configured to:

detect that the data bus clock is paused; and

place the core in a second low power mode, wherein the core does not remain active in the second low power mode so as to further reduce power consumption.

13. The system of claim 11, wherein the core is further configured to:

wake up the peripheral component; and

determine a reason for waking up the peripheral component.

14. The system of claim 11, wherein the core is further configured to:

wake up the peripheral component;

determine a reason for waking up the peripheral component; and

determine whether the data bus clock is paused after waking up the peripheral component.

15. The system of claim 11, wherein the data bus is configured to conform to a SLIMbus™

architecture.

16. The system of claim 11, wherein the core comprises a SLIMbus™

core.

17. The system of claim 11, further comprising:

a host component having a manager configured to;

receive a request for deactivation of the at least one data channel;

deactivate the at least one data channel;

determine that the data bus is inactive;

place the data bus in a third low power mode by pausing the data bus clock; and

entering an idle mode configured to further reduce power consumption.

18. The system of claim 17, wherein the manager comprises a SLIMbus™

manager.

19. A method for execution by a manager of a host component to provide power management for a data bus in a electronic device, the method comprising:

receiving a request for deactivation of at least one data channel;

deactivating the at least one data channel;

determining that the data bus is inactive;

placing the data bus in a low power mode by pausing a data bus clock; and

entering an idle mode configured to further reduce power consumption.

20. The method of claim 19, further comprising:

detecting that the data bus clock has been resumed; and

activating another at least one data channel.