INTERRUPTION, AT LEAST IN PART, OF FRAME TRANSMISSION

• US 20120002680A1
• Filed: 06/30/2010
• Published: 01/05/2012
• Est. Priority Date: 06/30/2010
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Louzoun, Eliel, Naouri, Ygdal
• Granted Patent: US 8,953,631 B2
• Time in Patent Office: Days
• US Class Current: 370/428
• CPC Class Codes: H04L 47/245 using preemption
• CPC Class Codes: H04L 47/263 Rate modification at the source after receiving feedback

Abstract

An embodiment may include circuitry to permit interruption, at least in part, of a first frame from a sender to an intended recipient in favor of transmitting, at least in part, a payload of a second frame from the sender to the intended recipient, and/or processing, at least in part, one or more incoming flow control notifications. The payload may be transmitted, at least in part, to the intended recipient in one or more frame fragments. Many modifications, variations, and alternatives are possible without departing from this embodiment.

Claims

1. An apparatus comprising:

circuitry to permit interruption, at least in part, of transmission, at least in part, of a first frame from a sender to an intended recipient in favor of at least one of;

transmitting, at least in part, a payload of a second frame from the sender to the intended recipient, the payload to be transmitted, at least in part, to the intended recipient in one or more frame fragments; and

processing, at least in part, one or more incoming flow control notifications.

2. The apparatus of claim 1, wherein:

the circuitry is to indicate, at least in part, the interruption of the transmission, at least in part, of the first frame, by issuing, at least in part, one or more control frames to the intended recipient, the one or more frame fragments being indicated, at least in part, by one or more predetermined values comprised, at least in part, in the one or more frame fragments;

the one or more control frames comprise at least one of;

one or more Ethernet pause frames;

one or more Ethernet priority flow control frames; and

the one or more control frames comprise one or more field values that indicate, at least in part, that the transmission, at least in part, of the first frame is to be interrupted in favor of the transmitting, at least in part, of the payload.

3. The apparatus of claim 2, wherein:

the one or more predetermined values are comprised, at least in part, in one or more cyclical redundancy check (CRC) fields in the one or more frame fragments; and

the one or more field values comprise one or more predetermined op codes.

4. The apparatus of claim 1, wherein:

the sender is to transmit, at least in part, the one or more frame fragments to the intended recipient via a switch;

the switch includes ingress ports and an egress port, at least one of the ingress ports to receive, at least in part, the one or more frame fragments, the egress port to send, at least in part, the one or more frame fragments to the intended recipient;

prior to receiving a first one of the one or more frame fragments, the ingress ports are to operate in a cut-through mode of operation with respect to the egress port; and

after receiving the first one of the one or more frame fragments, the ingress ports are to operate in a store-and-forward mode of operation with respect to the egress port.

5. The apparatus of claim 4, wherein:

the switch is to transmit, at least in part, one or more other frame fragments;

one or more other frame fragments have an identical priority as the second frame; and

the switch is to distinguish, at least in part, between the frame fragments based at least in part upon respective information comprised in the frame fragments, the respective information identifying, at least in part, one or more respective flows.

6. The apparatus of claim 1, wherein:

a circuit card includes, at least in part, the circuitry;

the circuit card is to be coupled to a circuit board in a first host;

the circuit board includes memory and a host processor; and

the circuitry is to receive, at least in part, the payload from the memory via one or more direct memory access operations.

7. The apparatus of claim 1, wherein:

the circuitry is to indicate, at least in part, the interruption of the transmission, at least in part, of the first frame, by issuing, at least in part, one or more control frames to the intended recipient, the one or more frame fragments being indicated, at least in part, by one or more predetermined values comprised, at least in part, in the one or more frame fragments;

the one or more predetermined values are comprised, at least in part, in one or more cyclical redundancy check (CRC) fields in the one or more frame fragments, the one or more predetermined values comprising one or more incorrect CRC values for the one or more frame fragments; and

the one or more frame fragments also comprise one or more other CRC fields that contain, at least in part, one or more accumulated CRC values for the one or more frame fragments.

22. The apparatus of claim 1, wherein:

the circuitry is to indicate, at least in part, the interruption of the transmission, at least in part, of the first frame, by issuing, at least in part, one or more control frames to the intended recipient, the one or more frame fragments being indicated, at least in part, by one or more predetermined values;

the one or more predetermined values comprise at least one of;

one or more ordered sets; and

one or more inverted cyclical redundancy check values.

8. Computer-readable memory storing one or more instructions that when executed by a machine result in performance of operations comprising:

permitting interruption, at least in part, of transmission, at least in part, of a first frame from a sender to an intended recipient in favor of at least one of;

transmitting, at least in part, a payload of a second frame from the sender to the intended recipient, the payload to be transmitted, at least in part, to the intended recipient in one or more frame fragments; and

processing, at least in part, one or more incoming flow control notifications.

9. The memory of claim 8, wherein:

the operations also comprise indicating, at least in part, the interruption of the transmission, at least in part, of the first frame, by issuing, at least in part, one or more control frames to the intended recipient, the one or more frame fragments being indicated, at least in part, by one or more predetermined values comprised, at least in part, in the one or more frame fragments;

the one or more control frames comprise at least one of;

one or more Ethernet pause frames;

one or more Ethernet priority flow control frames; and

the one or more control frames comprise one or more field values that indicate, at least in part, that the transmission, at least in part, of the first frame is to be interrupted in favor of the transmitting, at least in part, of the payload.

10. The memory of claim 9, wherein:

the one or more predetermined values are comprised, at least in part, in one or more cyclical redundancy check (CRC) fields in the one or more frame fragments; and

the one or more field values comprise one or more predetermined op codes.

11. The memory of claim 8, wherein:

the sender is to transmit, at least in part, the one or more frame fragments to the intended recipient via a switch;

the switch includes ingress ports and an egress port, at least one of the ingress ports to receive, at least in part, the one or more frame fragments, the egress port to send, at least in part, the one or more frame fragments to the intended recipient;

prior to receiving a first one of the one or more frame fragments, the ingress ports are to operate in a cut-through mode of operation with respect to the egress port; and

after receiving the first one of the one or more frame fragments, the ingress ports are to operate in a store-and-forward mode of operation with respect to the egress port.

12. The memory of claim 11, wherein:

the switch is to transmit, at least in part, one or more other frame fragments;

one or more other frame fragments have an identical priority as the second frame; and

the switch is to distinguish, at least in part, between the frame fragments based at least in part upon respective information comprised in the frame fragments, the respective information identifying, at least in part, one or more respective flows.

13. The memory of claim 8, wherein:

a circuit card includes, at least in part, the circuitry;

the circuit card is to be coupled to a circuit board in a first host;

the circuit board includes memory and a host processor; and

the circuitry is to receive, at least in part, the payload from the memory via one or more direct memory access operations.

14. The memory of claim 8, wherein:

the operations also comprise indicating, at least in part, the interruption of the transmission, at least in part, of the first frame, by issuing, at least in part, one or more control frames to the intended recipient, the one or more frame fragments being indicated, at least in part, by one or more predetermined values comprised, at least in part, in the one or more frame fragments;

the one or more predetermined values are comprised, at least in part, in one or more cyclical redundancy check (CRC) fields in the one or more frame fragments, the one or more predetermined values comprising one or more incorrect CRC values for the one or more frame fragments; and

the one or more frame fragments also comprise one or more other CRC fields that contain, at least in part, one or more accumulated CRC values for the one or more frame fragments.

15. A method comprising:

permitting interruption, at least in part, of transmission, at least in part, of a first frame from a sender to an intended recipient in favor of at least one of;

transmitting, at least in part, a payload of a second frame from the sender to the intended recipient, the payload to be transmitted, at least in part, to the intended recipient in one or more frame fragments; and

processing, at least in part, one or more incoming flow control notifications.

16. The method of claim 15, wherein:

the method also comprises indicating, at least in part, the interruption of the transmission, at least in part, of the first frame, by issuing, at least in part, one or more control frames to the intended recipient, the one or more frame fragments being indicated, at least in part, by one or more predetermined values comprised, at least in part, in the one or more frame fragments;

the one or more control frames comprise at least one of;

one or more Ethernet pause frames;

one or more Ethernet priority flow control frames; and

the one or more control frames comprise one or more field values that indicate, at least in part, that the transmission, at least in part, of the first frame is to be interrupted in favor of the transmitting, at least in part, of the payload.

17. The method of claim 16, wherein:

the one or more predetermined values are comprised, at least in part, in one or more cyclical redundancy check (CRC) fields in the one or more frame fragments; and

the one or more field values comprise one or more predetermined op codes.

18. The method of claim 15, wherein:

the sender is to transmit, at least in part, the one or more frame fragments to the intended recipient via a switch;

the switch includes ingress ports and an egress port, at least one of the ingress ports to receive, at least in part, the one or more frame fragments, the egress port to send, at least in part, the one or more frame fragments to the intended recipient;

prior to receiving a first one of the one or more frame fragments, the ingress ports are to operate in a cut-through mode of operation with respect to the egress port; and

after receiving the first one of the one or more frame fragments, the ingress ports are to operate in a store-and-forward mode of operation with respect to the egress port.

19. The method of claim 18, wherein:

the switch is to transmit, at least in part, one or more other frame fragments;

one or more other frame fragments have an identical priority as the second frame; and

the switch is to distinguish, at least in part, between the frame fragments based at least in part upon respective information comprised in the frame fragments, the respective information identifying, at least in part, one or more respective flows.

20. The method of claim 15, wherein:

a circuit card includes, at least in part, the circuitry;

the circuit card is to be coupled to a circuit board in a first host;

the circuit board includes memory and a host processor; and

the circuitry is to receive, at least in part, the payload from the memory via one or more direct memory access operations.

21. The method of claim 15, wherein:

the method also comprises indicating, at least in part, the interruption of the transmission, at least in part, of the first frame, by issuing, at least in part, one or more control frames to the intended recipient, the one or more frame fragments being indicated, at least in part, by one or more predetermined values comprised, at least in part, in the one or more frame fragments;

the one or more predetermined values are comprised, at least in part, in one or more cyclical redundancy check (CRC) fields in the one or more frame fragments, the one or more predetermined values comprising one or more incorrect CRC values for the one or more frame fragments; and

the one or more frame fragments also comprise one or more other CRC fields that contain, at least in part, one or more accumulated CRC values for the one or more frame fragments.