POWER LAYER GENERATION OF INVERTER GATE DRIVE SIGNALS

• US 20120014147A1
• Filed: 07/16/2010
• Published: 01/19/2012
• Est. Priority Date: 07/16/2010
• Status: Active Grant

• Current Assignee: Rockwell Automation Technologies Incorporated (Allen-Bradley Co., Inc.)
• Original Assignee: Rockwell Automation Technologies Incorporated (Allen-Bradley Co., Inc.)
• Inventors: Radosevich, Richard H.
• Granted Patent: US 8,575,882 B2
• Time in Patent Office: Days
• US Class Current: 363/71
• CPC Class Codes: H02M 1/0043 Converters switched with a phase shift, i.e. interleaved non-isolated DC/DC converters H02M3/1586
• CPC Class Codes: H02M 1/0845 digitally controlled (or with digital control)
• CPC Class Codes: H02M 1/385 with means for correcting output voltage deviations introduced by the dead time
• CPC Class Codes: H02M 7/493 the static converters being arranged for operation in parallel
• CPC Class Codes: H02M 7/539 with automatic control of output wave form or frequency H02M7/5375 - H02M7/5387 take precedence
• CPC Class Codes: H02M 7/81 arranged for operation in parallel
• CPC Class Codes: H02P 27/06 using dc to ac converters or inverters H02P27/05 takes precedence

Abstract

Solid state switches of inverters are controlled by timing signals computed in power layer interface circuitry for individual inverters. Multiple inverters may be placed in parallel with common three-phase output. Common control circuitry generates timing signals or data used to reconstruct the common signals and sends these signals to the power layer interface circuitry. A processor in a power layer interface circuitry used these signals to recomputed the timing signals. Excellent synchronicity may be provided between parallel inverters that each separately reconstruct the timing signals based upon the identical received data.

Claims

1. A system for controlling operation of power inverter switches, comprising:

control circuitry configured to generate signals for timing of state changes of the switches;

a data conductor coupled to the control circuitry for conveying the signals from the control circuitry;

power layer circuitry coupled to the data conductor and configured to receive the signals and to recompute the timing for the state changes based upon the received signals; and

a plurality of solid state switches coupled to the power layer circuitry and configured to change state to convert input power to controlled output power based upon the recomputed timing.

2. The system of claim 1, wherein the signals include a carrier signal and power phase compare signals.

3. The system of claim 1, wherein the signals include a deadtime signal.

4. The system of claim 1, wherein the data conductor comprises two optical fibers.

5. The system of claim 4, wherein a first optical fiber is dedicated to transmitting signals from the control circuitry to the power layer circuitry, and a second optical fiber is dedicated to transmitting signals from the power layer circuitry to the control circuitry.

6. The system of claim 5, wherein the power layer circuitry transmits, over the second optical fiber, at least signals representative of power phase current.

7. The system of claim 6, wherein the power layer circuitry also transmits, over the second optical fiber, signals representative of at least one of temperature, bus voltage, and fault status.

8. The system of claim 1, wherein the data conductor comprises three optical fibers, at least one of the optical fibers transmitting a clock signal from the control circuitry to the power layer circuitry.

9. The system of claim 1, wherein the power layer circuitry comprises a processing circuit configured to recompute the timing for the solid state switches based upon the received signals.

10. A system for controlling operation of power inverter switches, comprising:

control circuitry configured to generate signals for timing of state changes of the switches;

a plurality of inverters coupled to the control circuitry in parallel, the output of the inverters being coupled to provide a common 3-phase output, each inverter comprising power layer circuitry and a plurality of solid state switches coupled to the power layer circuitry; and

a plurality of fiber optic cables, one cable coupled between the control circuitry the power layer circuitry of each inverter for conveying the signals from the control circuitry to the respective power layer circuitry;

wherein power layer circuitry of each inverter is configured to receive the signals and to recompute the timing for the state changes based upon the received signals to control state changes of the solid state switches of the respective inverter to convert input power to controlled output power based upon the recomputed timing.

11. The system of claim 10, wherein timing for switching of the solid state switches of the inverters do not deviate from one another by more than approximately 40 ns.

12. The system of claim 10, wherein the signals include a carrier signal and power phase compare signals.

13. The system of claim 12, wherein the signals include a deadtime signal.

14. The system of claim 10, wherein each fiber optic cable comprises two optical fibers.

15. The system of claim 14, wherein a first optical fiber of each fiber optic cable is dedicated to transmitting signals from the control circuitry to the power layer circuitry, and a second optical fiber of each fiber optic cable is dedicated to transmitting signals from the power layer circuitry to the control circuitry.

16. The system of claim 15, wherein the power layer circuitry transmits, over the second optical fiber, at least signals representative of power phase current.

17. The system of claim 16, wherein the power layer circuitry also transmits, over the second optical fiber, signals representative of at least one of temperature, bus voltage, and fault status.

18. The system of claim 10, wherein each fiber optic cable comprises three optical fibers, at least one of the optical fibers of each fiber optic cable transmitting a clock signal from the control circuitry to the power layer circuitry.

19. The system of claim 10, wherein the power layer circuitry of each inverter comprises a processing circuit configured to recompute the timing for the solid state switches based upon the received signals.

20. The system of claim 10, wherein each of the fiber optic cables is approximately the same length.

21. A method for controlling operation of power inverter switches, comprising:

generating, in common control circuitry, signals for timing of state changes of the switches;

transmitting the signals to a plurality of inverters coupled to the control circuitry in parallel, the output of the inverters being coupled to provide a common 3-phase output, each inverter comprising power layer circuitry and a plurality of solid state switches coupled to the power layer circuitry;

recomputing, in the power layer circuitry of each inverter, the timing for the state changes based upon the received signals; and

controlling, via the power layer circuitry of each inverter, state changes of the solid state switches of the respective inverter to convert input power to controlled output power based upon the recomputed timing.

22. The method of claim 21, wherein the signals are transmitted from the common control circuitry to the plurality of inverters via fiber optic cables of substantially equal length.

23. The method of claim 21, wherein timing for switching of the solid state switches of the inverters do not deviate from one another by more than approximately 40 ns.

24. The method of claim 21, wherein the signals include a carrier signal, a deadtime signal, and power phase compare signals.

25. The method of claim 21, wherein each fiber optic cable comprises two optical fibers.

26. The method of claim 25, wherein a first optical fiber of each fiber optic cable is dedicated to transmitting signals from the control circuitry to the power layer circuitry, and a second optical fiber of each fiber optic cable is dedicated to transmitting signals from the power layer circuitry to the control circuitry.

27. The method of claim 26, wherein the power layer circuitry transmits, over the second optical fiber, at least signals representative of power phase current.

28. A system for controlling operation of power inverter switches, comprising:

master control circuitry configured to generate signals for timing of state changes of the switches and to transmit data to at least one slave power layer circuit;

at least one slave power layer circuit coupled to the master control circuitry and configured to regenerate the signals for timing of the state changes of the switches based upon the transmitted data.

29. The system of claim 28, comprising a plurality of slave power layer circuits for a respective plurality of inverters.

30. The system of claim 29, wherein the master control circuitry is configured to transmit the same data to all of the slave power layer circuits at substantially the same time, and wherein all of the slave power layer circuits are configured to regenerate substantially the same signals for timing of state changes of the switches of their respective inverter based upon the transmitted data at substantially the same time.