SEMICONDUCTOR MEMORY DEVICE AND METHOD OF DRIVING THE SAME

• US 20120014163A1
• Filed: 07/11/2011
• Published: 01/19/2012
• Est. Priority Date: 07/16/2010
• Status: Active Grant

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Yamazaki, Shinobu, Ohta, Yoshiji, Ishihara, Kazuya, Nakura, Mitsuru, Kawabata, Suguru, Awaya, Nobuyoshi
• Granted Patent: US 8,482,956 B2
• Time in Patent Office: Days
• US Class Current: 365/148
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0026 Bit-line or column circuits
• CPC Class Codes: G11C 13/0038 Power supply circuits
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0071 Write using write potential applied to access device gate
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: G11C 2213/82 Array having, for accessing a cell, a word line, a bit line and a plate or source line receiving different potentials
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

A semiconductor memory device includes a memory cell array where a plurality of memory cells are arranged in a matrix, each of the memory cells serially connecting a two-terminal type memory element and a transistor for selection, a first voltage applying circuit that applies a write voltage pulse to a bit line, and a second voltage applying circuit that applies a precharge voltage to a bit line and a common line. In writing the memory cell, after the second voltage applying circuit has both terminals of the memory cell previously precharged to the same voltage, the first voltage applying circuit applies the write voltage pulse to one terminal of the writing target memory cell via the bit line, and while the write voltage pulse is applied, the second voltage applying circuit maintains the application of the precharge voltage to the other terminal of the memory cell via the common line.

Claims

1. A semiconductor memory device comprising:

a memory cell array formed of a plurality of memory cells being arranged in column and row directions in a matrix, each of the plurality of memory cells including a memory element and a cell transistor, the memory element having two input/output terminals and storing information by a difference in an electrical property between the two terminals, in which the stored information is written by applying a voltage between the two terminals, the cell transistor having two input/output terminals and one control terminal, one terminal of the input/output terminals of the memory element being connected to one terminal of the input/output terminals of the cell transistor;

word lines extending in the column direction and respectively connecting the control terminals of the cell transistors of the memory cells arranged in the same column;

bit lines extending in the row direction and connecting the other terminals of the input/output terminals, which do not connect with the cell transistors, of the memory elements of the memory cells arranged in the same row;

a common line extending in the column or the row direction, and connecting the other terminals of the input/output terminals, which do not connect with the memory elements, of the cell transistors of the memory cells;

a word line voltage applying circuit that applies a voltage to a word line connected to the memory cell selected as a writing target in the writing of the information stored in the memory element;

a first voltage applying circuit that applies a write voltage to the bit line connected to the selected memory cell; and

a second voltage applying circuit that previously applies an identical precharge voltage to both of the bit line and the common line connected to the selected memory cell prior to applying the write voltage, and that applies the precharge voltage to the common line connected to the selected memory cell while the write voltage is applied to the bit line connected to the selected memory cell.

2. The semiconductor memory device according to claim 1, wherein

the second voltage applying circuit includes a precharge power line to which the precharge voltage is applied, and

the precharge power line is directly connected to the common line, and is connected to the respective bit lines via first transistors that are provided for each of the bit lines.

3. The semiconductor memory device according to claim 1, wherein

the first voltage applying circuit includes a write power line to which the write voltage is applied, and

the write power line is connected to the respective bit lines via second transistors that are provided for each of the bit lines.

4. The semiconductor memory device according to claim 1, wherein

the first voltage applying circuit includes a first write power line and a second write power line to which the write voltage having a different application voltage from the precharge voltage is respectively applied.

5. The semiconductor memory device according to claim 1, wherein

in the writing of the information stored in the memory element,

a first writing operation of writing the electrical property of the memory element from a first state to a second state, and a second writing operation of writing the electrical property of the memory element from the second state to the first state are included, and

the precharge voltage applied by the second voltage applying circuit in the first writing operation is identical to that in the second writing operation.

6. The semiconductor memory device according to claim 1, wherein

in the writing of the information stored in the memory element,

a first writing operation of writing the electrical property of the memory element from a first state to a second state, and a second writing operation of writing the electrical property of the memory element from the second state to the first state are included, and

the precharge voltage applied by the second voltage applying circuit in the first writing operation is different from that in the second writing operation.

7. The semiconductor memory device according to claim 1, wherein

in the writing of the information stored in the memory element,

a first writing operation of writing the electrical property of the memory element from a first state to a second state having a lower resistance than the first state, and a second writing operation of writing the electrical property of the memory element from the second state to the first state are included,

a polarity of the write voltage with respect to the precharge voltage in the first writing operation is different from that in the second writing operation, and

a voltage difference between a word line voltage applied to the word line connected to the selected memory cell and a lower one of the precharge voltage and the write voltage in the first writing operation is smaller than a voltage difference between the word line voltage and a lower one of the precharge voltage and the write voltage in the second writing operation.

8. The semiconductor memory device according to claim 7, wherein

the word line voltage applied by the word line voltage applying circuit in the first writing operation is identical to that in the second writing operation.

9. The semiconductor memory device according to claim 8, wherein

in the writing of the information stored in the plurality of memory elements,

a plurality of the memory cells connected to the selected word line are selected, and the first writing operation or the second writing operation is performed consecutively on the plurality of memory cells.

10. The semiconductor memory device according to claim 7, wherein

the precharge voltage applied by the second voltage applying circuit in the first writing operation is identical to that in the second writing operation.

11. The semiconductor memory device according to claim 1, wherein

the memory element is a bipolar variable resistance element in which a resistance state expressed by a resistance property between the two input/output terminals of the memory element reversibly transitions by applying voltages having different polarities.

12. A semiconductor memory device comprising:

a memory cell array formed of a plurality of memory cells being arranged in column and row directions in a matrix, each of the plurality of memory cells including a memory element and a cell transistor, the memory element having two input/output terminals and storing information by a difference in an electrical property between the two terminals, in which the stored information is written by applying a voltage between the two terminals, the cell transistor having two input/output terminals and one control terminal, one terminal of the input/output terminals of the memory element being connected to one terminal of the input/output terminals of the cell transistor;

word lines extending in the column direction and respectively connecting the control terminals of the cell transistors of the memory cells arranged in the same column;

bit lines extending in the row direction and connecting the other terminals of the input/output terminals, which do not connect with the memory elements, of the cell transistors of the memory cells arranged in the same row;

a common line extending in the column or row direction and connecting the other terminals of the input/output terminals, which do not connect with the cell transistors, of the memory elements of the memory cells;

a word line voltage applying circuit that applies a voltage to a word line connected to the memory cell selected as a writing target in the writing of the information stored in the memory element;

a first voltage applying circuit that applies a write voltage to the bit line connected to the selected memory cell; and

a second voltage applying circuit that previously applies an identical precharge voltage to both of the bit line and the common line connected to the selected memory cell prior to application of the write voltage, and that applies the precharge voltage to the common line connected to the selected memory cell while the write voltage is applied to the bit line connected to the selected memory cell, wherein

in the writing of the information stored in the memory element,

a first writing operation of writing the electrical property of the memory element from a first state to a second state, and a second writing operation of writing the electrical property of the memory element from the second state to the first state are included, and

the precharge voltage applied by the second voltage applying circuit in the first writing operation is different from that in the second writing operation.

13. The semiconductor memory device according to claim 12, wherein

the second voltage applying circuit includes a precharge power line to which the precharge voltage is applied, and

the precharge power line is directly connected to the common line, and is connected to the respective bit lines via first transistors that are provided for each of the bit lines.

14. The semiconductor memory device according to claim 12, wherein

the memory element is a bipolar variable resistance element in which a resistance state expressed by a resistance property between the two input/output terminals of the memory element reversibly transitions by applying voltages having different polarities.

15. A method of driving a semiconductor memory device,

the semiconductor memory device including:

a memory cell array formed of a plurality of memory cells being arranged in column and row directions in a matrix, each of the plurality of memory cells including a memory element and a cell transistor, the memory element having two input/output terminals and storing information by a difference in an electrical property between the two terminals, in which the stored information is written by applying a voltage between the two terminals, the cell transistor having two input/output terminals and one control terminal, one terminal of the input/output terminals of the memory element being connected to one terminal of the input/output terminals of the cell transistor;

word lines extending in the column direction and respectively connecting the control terminals of the cell transistors of the memory cells arranged in the same column;

bit lines extending in the row direction and connecting the other terminals of the input/output terminals, which do not connect with the cell transistors, of the memory elements of the memory cells arranged in the same row; and

a common line extending in the column or the row direction, and connecting the other terminals of the input/output terminals, which do not connect with the memory elements, of the cell transistors of the memory cells,

the method comprising;

in the writing of the information stored in the memory element,

a word line voltage applying step of selecting the memory cell that is a writing target and applying a word line voltage to the word line connected to the selected memory cell;

a precharging step of previously applying an identical precharge voltage to both of the bit line and the common line connected to the selected memory cell prior to application of a write voltage; and

a writing step of applying the write voltage to the bit line connected to the selected memory cell and maintaining the application of the precharge voltage to the common line connected to the selected memory cell during the application of the write voltage.

16. The method of driving a semiconductor memory device according to claim 15, wherein

the semiconductor memory device includes a first voltage applying circuit for applying the write voltage to the bit line connected to the selected memory cell and a second voltage applying circuit for applying the precharge voltage to the bit line and the common line connected to the selected memory cell,

the second voltage applying circuit includes a precharge power line that is directly connected to the common line, and is connected to the respective bit lines via first transistors that are provided for each of the bit lines,

in the precharging step, the precharge voltage is applied to both of the bit line and the common line via the precharge power line by making the first transistor connected to the bit line connected to the selected memory cell be in an ON state, and

in the writing step, the precharge voltage is applied to the common line via the precharge power line by making the first transistor connected to the bit line connected to the selected memory cell be in an OFF state.

17. The method of driving a semiconductor memory device according to claim 15, wherein

in the writing of the information stored in the memory element,

the precharge voltage applied in the precharging step and the writing step in a case of writing the electrical property of the memory element from a first state to a second state is identical to that in a case of writing the electrical property of the memory element from the second state to the first state.

18. The method of driving a semiconductor memory device according to claim 15, wherein

in the writing of the information stored in the memory element,

the precharge voltage applied in the precharging step and the writing step in a case of writing the electrical property of the memory element from a first state to a second state is different from that in a case of writing the electrical property of the memory element from the second state to the first state.

19. The method of driving a semiconductor memory device according to claim 15, wherein

in the writing step, one of a resistance lowering step of writing the electrical property of the memory element from a first state to a second state having a lower resistance than the first state and a resistance increasing step of writing the electrical property of the memory element from the second state to the first state is performed to each of the memory cells selected as the writing target,

a polarity of the write voltage with respect to the precharge voltage in the resistance lowering step is different from that in the resistance increasing step, and

a voltage difference between the word line voltage and a lower one of the precharge voltage and the write voltage in the resistance lowering step is smaller than a voltage difference between the word line voltage and a lower one of the precharge voltage and the write voltage in the resistance increasing step.

20. The method of driving a semiconductor memory device according to claim 19, wherein

the word line voltage applied in the word line voltage applying step in a case of performing the resistance lowering step is identical to that in a case of performing the resistance increasing step.

21. The method of driving a semiconductor memory device according to claim 20, wherein

in the word line voltage applying step, a plurality of the memory cells connected to the selected word line are selected, and

the method further including a step of performing the resistance lowering step or the resistance increasing step consecutively on the plurality of memory cells.

22. The method of driving a semiconductor memory device according to claim 19, wherein

the precharge voltage applied in the precharging step and the writing step in a case of performing the resistance lowering step is identical to that in a case of performing the resistance increasing step.

23. The method of driving a semiconductor memory device according to claim 15, wherein

the memory element is a bipolar variable resistance element in which a resistance state expressed by a resistance property between the two input/output terminals of the memory element reversibly transitions by applying voltages having different polarities.

24. A method of driving a semiconductor memory device,

the semiconductor memory device including:

a memory cell array formed of a plurality of memory cells being arranged in column and row directions in a matrix, each of the plurality of memory cells including a memory element and a cell transistor, the memory element having two input/output terminals and storing information by a difference in an electrical property between the two terminals, in which the stored information is written by applying a voltage between the two terminals, the cell transistor having two input/output terminals and one control terminal, one terminal of the input/output terminals of the memory element being connected to one terminal of the input/output terminals of the cell transistor;

word lines extending in the column direction and respectively connecting the control terminals of the cell transistors of the memory cells arranged in the same column;

bit lines extending in the row direction and connecting the other terminals of the input/output terminals, which do not connect with the memory elements, of the cell transistors of the memory cells arranged in the same row; and

a common line extending in the column or the row direction and connecting the other terminals of the input/output terminals, which do not connect with the cell transistors, of the memory elements of the memory cells,

the method comprising;

in the writing of the information stored in the memory element,

a word line voltage applying step of selecting the memory cell that is a writing target and applying a word line voltage to the word line connected to the selected memory cell;

a precharging step of previously applying an identical precharge voltage to both of the bit line and the common line connected to the selected memory cell prior to application of a write voltage; and

a writing step of applying the write voltage to the bit line connected to the selected memory cell and maintaining the application of the precharge voltage to the common line connected to the selected memory cell during the application of the write voltage, wherein

the precharge voltage applied in the precharging step and the writing step in a case of writing the electrical property of the memory element from a first state to a second state is different from that in a case of writing the electrical property of the memory element from the second state to the first state.

25. The method of driving a semiconductor memory device according to claim 24, wherein

the semiconductor memory device includes a first voltage applying circuit for applying the write voltage to the bit line connected to the selected memory cell and a second voltage applying circuit for applying the precharge voltage to the bit line and the common line connected to the selected memory cell,

the second voltage applying circuit includes a precharge power line that is directly connected to the common line, and is connected to the respective hit lines via first transistors that are provided for each of the bit lines,

in the precharging step, the precharge voltage is applied to both of the bit line and the common line via the precharge power line by making the first transistor connected to the bit line connected to the selected memory cell be in an ON state, and

in the writing step, the precharge voltage is applied to the common line via the precharge power line by making the first transistor connected to the bit line connected to the selected memory cell be in an OFF state.

26. The method of driving a semiconductor memory device according to claim 24, wherein

the memory element is a bipolar variable resistance element in which a resistance state expressed by a resistance property between the two input/output terminals of the memory element reversibly transitions by applying voltages having different polarities.