METHOD AND SYSTEM FOR UTILIZING LOW POWER SUPERSPEED INTER-CHIP (LP-SSIC) COMMUNICATIONS

• US 20120017016A1
• Filed: 01/19/2011
• Published: 01/19/2012
• Est. Priority Date: 07/13/2010
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Ma, Kenneth, Lee, Seong-Ho
• Granted Patent: US 8,719,475 B2
• Time in Patent Office: Days
• US Class Current: 710/110
• CPC Class Codes: G06F 13/426 using an embedded synchronisation, e.g. Firewire bus, Fibre Channel bus, SSA bus
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Inter-chip connectivity may be provided in a computing device, which may comprise a USB host and at and at least one USB device embedded within the computing device, based on Universal Serial Bus version 3.0 (USB3.0) interface. In this regard, internal communication of data between the USB host and embedded USB device may be performed via USB3.0 SuperSpeed signals. The USB host and/or the USB3.0 interface may be configured to enable USB3.0 internal communication of data, and to reduce power consumption during the internal communication of data compared to external USB3.0 communications. Configuration of the USB3.0 interface for internal communication of data may comprises modifying and/or adjusting physical (PHY) layer, link layer, and/or protocol layer related parameters, functions, resources, and/or operations. The USB3.0 SuperSpeed signals may be communication using scalable low voltage signaling (SLVS). In this regard, Input/Output (IO) Swing may be set based on loopback training sequence.

Claims

1. A method, comprising:

in a computing device that comprises a Universal Serial Bus (USB) host and at least one USB slave device that is embedded within said computing device, wherein said computing device is operable to support use of Universal Serial Bus version 3.0 (USB3.0) interface;

configuring said USB host to utilize said USB3.0 interface during internal communication of data within said computing device, wherein said configuration comprises configuring one or more power consumption reduction parameters that control said USB host and/or said USB3.0 interface; and

internally communicating said data between said USB host and said embedded USB slave device using USB3.0 SuperSpeed signals based on said configuration.

2. The method according to claim 1, wherein said computing device comprises a personal computer, a laptop computer, a tablet computer, a server, a smartphone, or a handheld personal communication device.

3. The method according to claim 1, wherein said configuration comprises modifying and/or adjusting physical (PHY) layer, link layer, and/or protocol layer related parameters, functions, resources, and/or operations of said USB3.0 interface for said internal data communication.

4. The method according to claim 1, comprising communicating said USB3.0 SuperSpeed signals utilized during said internal communication of data between said USB host and said embedded USB slave device using scalable low voltage signaling (SLVS).

5. The method according to claim 1, comprising setting Input/Output (IO) Swing for said USB3.0 internal communication of data based on loopback training sequence.

7. The method according to claim 1, comprising modifying one or more link operation states during internal data communication, wherein said modification comprises turning off Phased Locked Loop (PLL) used for said USB3.0 SuperSpeed signals during U1 state.

8. The method according to claim 1, comprising setting shortest maximum trace length for target form-factor (FR) associated with said USB3.0 internal communication of data based on determination of type of said computing device.

9. The method according to claim 1, comprising disabling USB2.0 operations during communications with said at least one embedded USB device.

10. The method according to claim 9, wherein said disabling comprises removing USB2.0 related links, Physical (PHY) layer support, and/or Phased Locked Loop (PLLs), and/or disabling jump to one or more USB2.0 related states in USB state machines.

6. The method according to claim 6, comprising setting said IO Swing to a default value at start of said loopback training sequence;

and incrementing or decrementing said IO Swing based on determination of error during loopback communication.

11. A system, comprising:

one or more circuits for use in a computing device, said one or more circuits comprising a Universal Serial Bus (USB) host, at least one USB slave device that is embedded within said computing device, and a Universal Serial Bus version 3.0 (USB3.0) interface, said one or more circuits being operable to;

configure said USB host to utilize said USB3.0 interface during internal communication of data within said computing device, wherein said configuration comprises configuring one or more power consumption reduction parameters that control said USB host and/or said USB3.0 interface; and

internally communicate said data between said USB host and said embedded USB slave device using USB3.0 SuperSpeed signals based on said configuration.

12. The system according to claim 11, wherein said computing device comprises a personal computer, a laptop computer, a tablet computer, a server, a smartphone, or a handheld personal communication device.

13. The system according to claim 11, wherein said configuration comprises modifying and/or adjusting physical (PHY) layer, link layer, and/or protocol layer related parameters, functions, resources, and/or operations of said USB3.0 interface for said internal data communication.

14. The system according to claim 11, wherein said one or more circuits are operable to communicate said USB3.0 SuperSpeed signals utilized during said internal communication of data between said USB host and said embedded USB slave device using scalable low voltage signaling (SLVS).

15. The system according to claim 11, wherein said one or more circuits are operable to set Input/Output (IO) Swing for said USB3.0 internal communication of data based on loopback training sequence.

17. The system according to claim 11, wherein said one or more circuits are operable to modify one or more link operation states during internal data communication, wherein said modification comprises turning off Phased Locked Loop (PLL) used for said USB3.0 SuperSpeed signals during U1 state.

18. The system according to claim 11, wherein said one more circuit are operable to set shortest maximum trace length for target form-factor (FR) associated with said USB3.0 internal communication of data based on determination of type of said computing device.

19. The system according to claim 11, wherein said one or more circuits are operable to disable USB2.0 operations during communications with said at least one embedded USB device.

20. The system according to claim 19, wherein said disabling comprises removing USB2.0 related links, Physical (PHY) layer support, and/or Phased Locked Loop (PLLs), and/or disabling jump to one or more USB2.0 related states in USB state machines.

16. The system according to claim 16, wherein said one or more circuits are operable to set said IO Swing to a default value at start of said loopback training sequence;

and incrementing or decrementing said IO Swing based on determination of error during loopback communication.