NON-VOLATILE MEMORY WITH DYNAMIC MULTI-MODE OPERATION

• US 20120023285A1
• Filed: 09/22/2011
• Published: 01/26/2012
• Est. Priority Date: 02/16/2007
• Status: Active Grant

• Current Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Original Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Inventors: KIM, Jin-Ki
• Granted Patent: US 8,391,064 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7204 Capacity control, e.g. partitioning, end-of-life degradation
• CPC Class Codes: G06F 2212/7206 Reconfiguration of flash memory system
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 2211/5646 Multilevel memory with flag bits, e.g. for showing that a "first page" of a word line is programmed but not a "second page"

Abstract

A method and system for extending the life span of a flash memory device. The flash memory device is dynamically configurable to store data in the single bit per cell (SBC) storage mode or the multiple bit per cell (MBC) mode, such that both SBC data and MBC data co-exist within the same memory array. One or more tag bits stored in each page of the memory is used to indicate the type of storage mode used for storing the data in the corresponding subdivision, where a subdivision can be a bank, block or page. A controller monitors the number of program-erase cycles corresponding to each page for selectively changing the storage mode in order to maximize lifespan of any subdivision of the multi-mode flash memory device.

Claims

1. A method comprising:

receiving a request that includes a logical address;

mapping the logical address to a corresponding physical address within a flash memory array; and

issuing i) a first type of program command when the physical address is within a first subdivision of the flash memory array; and

ii) a second different type of program command when the physical address is within a second subdivision of the flash memory array, the first subdivision being different than the second subdivision.

2. The method of claim 1 wherein the first and second subdivisions each include a block, the block having a predetermined number of pages.

3. The method of claim 1 wherein at least one of the first and second subdivisions is a page of a memory block.

4. The method of claim 1 wherein the first type of program command is a Single Bit per Cell (SBC) storage mode specific command.

5. The method of claim 4 wherein the second type of program command is a Multiple Bit per Cell (MBC) storage mode specific command.

6. The method of claim 1 wherein the mapping includes a look up in an address mapping table storing mode tags.

7. The method of claim 1 wherein the method is carried out by a flash memory controller.

8. A method carried out within a flash memory device, the method comprising:

receiving a first external command;

decoding the first external command to issue a corresponding first internal control command to execute a first program operation in accordance with a first algorithm;

receiving a second external command; and

decoding the second external command to issue a corresponding second internal control command to execute a second program operation in accordance with a second algorithm, the first algorithm and the second algorithm each associated with different specific voltage levels and timings of control signals.

9. The method of claim 8 wherein the first program operation is a Single Bit per Cell (SBC) program operation.

10. The method of claim 9 wherein the second program operation is a Multiple Bit per Cell (MBC) program operation.

11. The method of claim 8 further comprising:

receiving a third external command;

decoding the third external command to issue a corresponding third internal control command to execute a first read operation in accordance with a third algorithm;

receiving a fourth external command; and

decoding the fourth external command to issue a corresponding fourth internal control command to execute a second read operation in accordance with a fourth algorithm, the third algorithm being different than the fourth algorithm.

12. The method of claim 11 wherein the first read operation is a Single Bit per Cell (SBC) read operation.

13. The method of claim 12 wherein the second read operation is a Multiple Bit per Cell (MBC) read operation.

14. A system comprising:

a flash memory device including a flash memory array having at least a first subdivision configured in a first storage mode and a second subdivision configured in a second storage mode, the first storage mode being different than the second storage mode; and

a controller configured to receive a request from a host system, the controller including a translator configured to map a logical address provided by the host system to a corresponding physical address in the flash memory device, the controller being further configured to issue a command to the flash memory device which is coupled to the controller, and

the flash memory device being configured to execute, in response to the command, a read or program operation in accordance with i) a first algorithm when the logical address corresponds to a first physical address within the first subdivision; and

ii) a second different algorithm when the logical address corresponds to a second physical address within the second subdivision.

15. The system of claim 14 wherein the first storage mode is a Single Bit per Cell (SBC) storage mode.

16. The system of claim 15 wherein the second storage mode is a Multiple Bit per Cell (MBC) storage mode.

17. The system of claim 14 wherein the controller is a flash memory controller.

18. The system of claim 14 wherein the translator is implemented as an address mapping table storing mode tags.

19. The system of claim 14 further comprising another flash memory device serially coupled to the flash memory device.

20. The system of claim 14 further comprising another flash memory device and common buses, the flash memory devices coupled in parallel with respect to the common buses.