Arrangement for Energy Conditioning

• US 20120023741A1
• Filed: 08/01/2011
• Published: 02/02/2012
• Est. Priority Date: 04/08/1997
• Status: Active Grant

• Current Assignee: Anthony A. Anthony, William M. Anthony
• Original Assignee: X2Y Attenuators, LLC
• Inventors: Anthony, Anthony A., Anthony, William M.
• Granted Patent: US 9,036,319 B2
• Time in Patent Office: Days
• US Class Current: 29/825
• CPC Class Codes: H01G 4/40 Structural combinations of fixed capacitors with other electric elements, the structure mainly consisting of a capacitor, e.g. RC combinations
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 23/585 comprising conductive layers or plates or strips or rods or rings H01L23/60, H01L23/62, H01L23/64, H01L23/66 take precedence
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/207 Diameter ranges
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H03H 2001/0014 Capacitor filters, i.e. capacitors whose parasitic inductance is of relevance to consider it as filter
• CPC Class Codes: H03H 2001/0085 : Multilayer, e.g. LTCC, HTCC, green sheets inside PCB filters H05K
• CPC Class Codes: Y10T 29/49117 : Conductor or circuit manufacturing

Abstract

Circuit arrangement embodiments that use relative groupings of energy pathways that include shielding circuit arrangements that can sustain and condition electrically complementary energy confluences.

Claims

1. A method for making a conductive pathway arrangement, comprising:

electrically isolating an upper pathway, a center pathway and a lower pathway from a first pathway and a second pathway;

separating by a first horizontal distance a first and a second perimeter edge portion of a bottom surface area of a superposed first pathway shielded area of a first pathway shielded area of said first pathway;

separating by a second horizontal distance a first and a second perimeter edge portion of a top surface area of a superposed second pathway shielded area of a second pathway shielded area of said second pathway;

electrically coupling an upper pathway shielding area that is larger in size than either said superposed first pathway shielded area or said superposed second pathway shielded area to a center pathway shielding area that is larger in size than either said superposed first pathway shielded area or said superposed second pathway shielded area;

electrically coupling said center pathway shielding area to a lower pathway shielding area that is larger in size than either said superposed first pathway shielded area or said superposed second pathway shielded area;

superposing with one another a top surface area of said superposed first pathway shielded area, said bottom surface area of said superposed first pathway shielded area, said top surface area of said superposed second pathway shielded area and a bottom surface area of said superposed second pathway shielded area, such that said first perimeter edge portion of said bottom surface area of said superposed first pathway shielded area and said first perimeter edge portion of said top surface area of said superposed second pathway shielded area are superposed with one another in a first superposed perimeter edge alignment.