REDUCTION OF INRUSH CURRENT DUE TO VOLTAGE SAGS WITH INPUT POWER VOLTAGE RECONNECTION AT ZERO CROSSING

• US 20120032662A1
• Filed: 10/14/2011
• Published: 02/09/2012
• Est. Priority Date: 10/24/2005
• Status: Active Grant

• Current Assignee: I-EWM Acquisation, LLC
• Original Assignee: Georgia Tech Research Corporation (University System of Georgia)
• Inventors: Divan, Deepakraj
• Granted Patent: US 9,065,266 B2
• Time in Patent Office: Days
• US Class Current: 323/293
• CPC Class Codes: H01H 9/542 Contacts shunted by static switch means
• CPC Class Codes: H01H 9/56 for ensuring operation of the switch at a predetermined point in the ac cycle
• CPC Class Codes: H02H 3/247 having timing means
• CPC Class Codes: H02H 9/001 limiting speed of change of electric quantities, e.g. soft switching on or off progressive control of electronic switches for eliminating interferences H03K17/16

Abstract

Various systems and methods are provided for minimizing an inrush current to a load after a voltage sag in a power voltage. In one embodiment, a method is provided comprising the steps of applying a power voltage to a load, and detecting a sag in the power voltage during steady-state operation of the load. The method includes the steps of adding an impedance to the load upon detection of the sag in the power voltage, and removing the impedance from the load when the power voltage has reached a predefined point in the power voltage cycle after the power voltage has returned to a nominal voltage.

Claims

1. A method, comprising:

applying a power voltage to a load;

detecting a sag in the power voltage during steady-state operation of the load;

adding an impedance to the load upon detection of the sag in the power voltage; and

removing the impedance from the load when the power voltage has reached a predefined point in the power voltage cycle after the power voltage has returned to a nominal voltage.

2. The method of claim 1, further comprising the step of timing the removal of the impedance from the load after the power voltage has returned to the nominal voltage so as to minimize an occurrence of an inrush current surge flowing to the load.

3. The method of claim 2, wherein the absolute value of the magnitude of the power voltage is less than the magnitude of a rectified voltage across a capacitor associated with a rectifier of the load at the predefined point in the power voltage cycle when the impedance is removed from the load.

4. The method of claim 1, wherein the power voltage is applied to an inductive load.

5. The method of claim 1, wherein the power voltage is applied to a rectifier/capacitor load.

6. The method of claim 1, wherein the impedance is removed from the load at approximately a zero crossing of the power voltage occurring after the power voltage has returned to the nominal voltage.

7. The method of claim 1, wherein the impedance is removed from the load at approximately a first one of a plurality of zero crossings occurring after the power voltage has returned to the nominal voltage.

8. The method of claim 1, wherein the impedance is removed from the load at a point on the power voltage cycle that substantially minimizes a differential between an absolute value of a magnitude of the power voltage and a magnitude of a rectified voltage across a capacitor associated with the load.

9. The method of claim 1, wherein the impedance is removed from the load at a point in the power voltage cycle where an absolute value of a magnitude of the power voltage is less than a magnitude of a rectified voltage across a capacitor associated with the load.

10. The method of claim 9, wherein at least one diode in a rectifier employed to convert the power voltage is reverse biased when the absolute value of the magnitude of the power voltage is less than the magnitude of the rectified voltage across the capacitor associated with the load.

11. An apparatus, comprising:

an impedance that is added to a load when a power voltage applied to the load experiences a sag during a steady-state operation of the load; and

a circuit configured to remove the impedance from the load when the power voltage has reached a predefined point in the power voltage cycle after the power voltage has returned to a nominal voltage.

12. The apparatus of claim 11, wherein the impedance is a predefined resistance.

13. The apparatus of claim 11, wherein the impedance comprises an infinite resistance associated with an open circuit.

14. The apparatus of claim 11, wherein the circuit is configured to time the removal of the impedance from the load after the power voltage has returned to the nominal voltage so as to minimize an occurrence of an inrush current surge flowing to the load.

15. The apparatus of claim 14, wherein the circuit is configured to time the removal of the impedance from the load when the absolute value of the magnitude of the power voltage is less than the magnitude of a rectified voltage across a capacitor associated with a rectifier of the load.

16. The apparatus of claim 11, wherein the load is an inductive load.

17. The apparatus of claim 11, wherein the load is a rectifier/capacitor load.

18. The apparatus of claim 11, wherein the circuit is configured to time the removal of the impedance from the load at approximately a zero crossing of the power voltage occurring after the power voltage has returned to the nominal voltage.

19. The apparatus of claim 11, wherein the circuit is configured to time the removal of the impedance from the load at a point on the power voltage cycle that substantially minimizes a differential between an absolute value of a magnitude of the power voltage and a magnitude of a rectified voltage across a capacitor associated with the load.

20. An apparatus, comprising:

means for adding an impedance a load upon a detection of a sag of a predefined duration in a power voltage applied to the load during a steady-state operation of the load; and

means for removing the impedance from the load when the power voltage has reached a predefined point in the power voltage cycle after the power voltage has returned to a nominal voltage.

21. The apparatus of claim 20, wherein the means for removing the impedance from the load further comprises means for timing the removal of the impedance from the load so as to substantially minimize an occurrence of an inrush current surge flowing to the load.

22. The apparatus of claim 21, wherein the means for timing the removal of the impedance from the load further times the removal of the impedance from the load when the absolute value of the magnitude of the power voltage is less than the magnitude of a rectified voltage across a capacitor associated with a rectifier of the load.