PCI EXPRESS ENHANCEMENTS AND EXTENSIONS
First Claim
1. An apparatus comprising:
- a first input/output (I/O) device adapted to be coupled to a serial point-to-point interconnect, the first I/O device including a local memory, wherein a first portion of the local memory is to be mapped into a host memory space, which is adapted to be visible to a host processor in a computer system, the first portion of the local memory mapped into the host memory space being adapted to be utilized as a window cache for accesses from the host processor to the first I/O device.
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Abstract
A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.
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Citations
4 Claims
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1. An apparatus comprising:
a first input/output (I/O) device adapted to be coupled to a serial point-to-point interconnect, the first I/O device including a local memory, wherein a first portion of the local memory is to be mapped into a host memory space, which is adapted to be visible to a host processor in a computer system, the first portion of the local memory mapped into the host memory space being adapted to be utilized as a window cache for accesses from the host processor to the first I/O device. - View Dependent Claims (2, 3, 4)
Specification