METHOD OF PROCESSING OF NITRIDE SEMICONDUCTOR WAFER, NITRIDE SEMICONDUCTOR WAFER, METHOD OF PRODUCING NITRIDE SEMICONDUCTOR DEVICE AND NITRIDE SEMICONDUCTOR DEVICE

• US 20120043645A1
• Filed: 11/02/2011
• Published: 02/23/2012
• Est. Priority Date: 02/27/2008
• Status: Active Grant

• Current Assignee: Sumitomo Electric Industries Limited (Sumitomo Corporation)
• Original Assignee: Sumitomo Electric Industries Limited (Sumitomo Corporation)
• Inventors: ISHIBASHI, Keiji, Mikami, Hidenori, Matsumoto, Naoki
• Granted Patent: US 8,183,669 B2
• Time in Patent Office: Days
• US Class Current: 257/615
• CPC Class Codes: C30B 29/403 AIII-nitrides
• CPC Class Codes: C30B 33/00 After-treatment of single crystals or homogeneous polycrystalline material with defined structure C30B31/00 takes precedence
• CPC Class Codes: H01L 21/02021 Edge treatment, chamfering
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/12041 LED
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 33/0075 comprising nitride compounds
• CPC Class Codes: Y10S 438/928 Front and rear surface processing
• CPC Class Codes: Y10S 438/959 Mechanical polishing of wafer
• CPC Class Codes: Y10S 438/977 Thinning or removal of substrate

Abstract

A nitride semiconductor wafer is planar-processed by grinding a bottom surface of the wafer, etching the bottom surface by, e.g., KOH for removing a bottom process-induced degradation layer, chamfering by a rubber whetstone bonded with 100 wt %-60 wt % #3000-#600 diamond granules and 0 wt %-40 wt % oxide granules, grinding and polishing a top surface of the wafer, etching the top surface for eliminating a top process-induced degradation layer and maintaining a 0.5 μm-10 μm thick edge process-induced degradation layer.

Claims

1-12. -12. (canceled)

13. A nitride semiconductor device comprising:

a substrate of a nitride semiconductor wafer which has a chamfered edge, a 0.5 μ

m-10 μ

m thick edge process-induced degradation layer with a deformed lattice structure remaining on the chamfered edge and a mirror-flat top surface;

nitride films epitaxially grown on the substrate; and

electrodes formed on the epitaxially grown layers.

14. The nitride semiconductor device as claimed in claim 13, wherein edge roughness of the substrate of the nitride semiconductor wafer is Ra0.07 μ

m to Ra3 μ

m.

15. The nitride semiconductor device as claimed in claim 13, wherein edge oxygen concentration of the substrate of the nitride semiconductor wafer is 3 at % to 20 at %.

16. The nitride semiconductor device as claimed in claim 13, wherein edge metal concentration of the substrate of the nitride semiconductor wafer is 0.1 at % to 5 at %.

17. A nitride semiconductor device comprising:

a substrate of a nitride semiconductor wafer having a chamfered edge formed by a rubber-bonding whetstone, a 1 μ

m-3 μ

m thick edge process-induced degradation layer with a deformed lattice structure remaining on the chamfered edge and a mirror-flat top surface;

nitride films epitaxially grown on the substrate; and

electrodes formed on the epitaxially grown layers.