METHOD FOR CONTROLLING WARPAGE WITHIN ELECTRONIC PRODUCTS AND AN ELECTRONIC PRODUCT

• US 20120048605A1
• Filed: 08/31/2010
• Published: 03/01/2012
• Est. Priority Date: 08/31/2010
• Status: Active Grant

• Current Assignee: GE Embedded Electronics Oy (General Electric Company)
• Original Assignee: Imbera Electronics Oy (General Electric Company)
• Inventors: CHUNG, Kwan Sik
• Granted Patent: US 9,420,694 B2
• Time in Patent Office: Days
• US Class Current: 174/258
• CPC Class Codes: H01L 2224/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 2924/3511 Warping
• CPC Class Codes: H05K 1/188 manufactured by mounting on or attaching to a structure having a conductive layer, e.g. a metal foil, such that the terminals of the component are connected to or adjacent to the conductive layer before embedding, and by using the conductive layer, which is patterned after embedding, at least partially for connecting the component
• CPC Class Codes: H05K 2201/09136 Means for correcting warpage
• CPC Class Codes: H05K 2203/063 of preperforated insulating layer
• CPC Class Codes: H05K 3/4626 characterised by the insulating layers or materials H05K3/4688 takes precedence
• CPC Class Codes: Y10T 29/49126 Assembling bases
• CPC Class Codes: Y10T 29/49155 Manufacturing circuit on or in base

Abstract

The present invention discloses a method for minimizing warpage in the electronic products, and the structures of such electronic products as well. Groove holes are formed into the insulating material layer or several layers. The groove holes can be processed by laser drilling or by other suitable means. A cured epoxy adhesive will fill the groove holes after the heat and pressure treatment performed to the circuit structure. The electronic product may contain several insulating layers and embedded electronic components connected to a wiring layer. A double-stacked symmetrical structure can also be manufactured. Asymmetrical structures with different sized embedded components can be handled as well. The groove holes can be shaped as straight short lines, ellipses, crosses, circles etc, or as any combination of different shapes. The groove holes can be scratched so that they locate outside strips, between the strips of a panel, between blocks of the strip, between modules of the block or between embedded components of the module.

Claims

1. An electronic product, comprising:

at least one wiring pattern layer;

at least one insulating material layer;

at least one embedded component connected to the wiring pattern layer;

wherein at least one insulating material layer comprises groove holes for decreasing warpage of the electronic product.

2. The electronic product according to claim 1, wherein the insulating material layer is an uncured, a semi-cured or a cured substrate layer.

3. The electronic product according to claim 1, wherein the insulating material layer comprises reinforced glass fibers.

4. The electronic product according to claim 1, further comprising:

cured epoxy adhesive filling the groove holes after heat and pressure treatment.

5. The electronic product according to claim 1, further comprising:

a first uncured or semi-cured epoxy layer placed on top of the wiring pattern layer;

a first cured epoxy layer placed on top of the first uncured or semi-cured epoxy layer;

a second uncured or semi-cured epoxy layer with the groove holes placed on top of the first cured epoxy layer; and

a second cured epoxy layer with the groove holes placed on top of the second uncured or semi-cured epoxy layer.

6. The electronic product according to claim 5, further comprising:

the second cured epoxy layer is manufactured without the groove holes.

7. The electronic product according to claim 6, further comprising:

the first cured epoxy layer comprises the groove holes.

8. The electronic product according to claim 6, further comprising:

a second wiring pattern layer is placed on top of the second uncured or semi-cured epoxy layer instead of the second cured epoxy layer.

9. The electronic product according to claim 1, further comprising:

a first uncured or semi-cured epoxy layer is placed on top of a first wiring pattern layer;

a first cured epoxy layer is placed on top of the first uncured or semi-cured epoxy layer;

a second uncured or semi-cured epoxy layer with the groove holes is placed on top of the first cured epoxy layer;

a second cured epoxy layer is placed on top of the second uncured or semi-cured epoxy layer;

an air gap on top of the second cured epoxy layer;

a third cured epoxy layer is placed on top of the air gap;

a third uncured or semi-cured epoxy layer with the groove holes is placed on top of the third cured epoxy layer;

a fourth cured epoxy layer is placed on top of the third uncured or semi-cured epoxy layer;

a fourth uncured or semi-cured epoxy layer is placed on top of the fourth cured epoxy layer; and

a second wiring pattern layer is placed on top of the fourth uncured or semi-cured epoxy layer.

10. The electronic product according to claim 1, further comprising:

a first uncured or semi-cured epoxy layer is placed on top of a first wiring pattern layer;

a first cured epoxy layer is placed on top of the first uncured or semi-cured epoxy layer;

a second uncured or semi-cured epoxy layer with the groove holes is placed on top of the first cured epoxy layer;

a temporary bonding means on top of the second uncured or semi-cured epoxy layer;

a third uncured or semi-cured epoxy layer with the groove holes is placed on top of the temporary bonding means;

a second cured epoxy layer is placed on top of the third uncured or semi-cured epoxy layer;

a fourth uncured or semi-cured epoxy layer is placed on top of the second cured epoxy layer; and

a second wiring pattern layer is placed on top of the fourth uncured or semi-cured epoxy layer.

11. The electronic product according to claim 5, wherein the embedded component is placed in an installation cavity of the first uncured or semi-cured epoxy layer, the first cured epoxy layer and the second uncured or semi-cured epoxy layer.

12. The electronic product according to claim 1, wherein the groove holes are shaped as longitudinal ellipses, transversal ellipses, circles, crosses, rotated crosses, lines, triangles, squares, polygons or as a combination of at least two of the shapes.

13. The electronic product according to claim 1, wherein at least one second embedded component is electrically connected to a second wiring pattern layer.

14. The electronic product according to claim 13, wherein at least one groove hole is between the first wiring pattern layer and the second wiring pattern layer.

15. The electronic product according to claim 1, wherein the groove holes locate outside strips and/or between strips of a panel and/or between blocks of a strip and/or between modules of a block and/or between embedded components of a module.

16. The electronic product according to claim 1, wherein the width of the groove holes is between 50 and 300 micrometers.

17. The electronic product according to claim 1, wherein the thickness of the insulating material layers is between 40 and 240 micrometers.

18. The electronic product according to claim 1, wherein the at least one embedded component is a semiconductor component, a microcircuit, a memory chip or a processor.

19. The electronic product according to claim 1, wherein the electronic product is an intermediate product such as a panel, a strip, a block or a module.

20. A method of manufacturing an electronic product with decreased warpage, the method comprising:

manufacturing at least one wiring pattern layer;

manufacturing at least one insulating material layer;

forming groove holes to at least one insulating material layer;

connecting at least one embedded component to the wiring pattern layer;

stacking the above layers on top of each other; and

curing the stacked layers together with heat and pressure treatment in order to achieve the electronic product with decreased warpage.

21. The method according to claim 20, further comprising:

forming the groove holes by laser drilling means.

22. The method according to claim 20, further comprising:

forming the groove holes by mechanical means, cutting means, boring means, chemical reacting means or etching means.

23. The method according to claim 20, further comprising:

placing the embedded component in an installation cavity formed in at least one insulating material layer.

24. The method according to claim 20, wherein the groove holes are shaped as longitudinal ellipses, transversal ellipses, circles, crosses, rotated crosses, lines, triangles, squares, polygons or as a combination of at least two of the shapes.

25. The method according to claim 20, further comprising:

forming the groove holes outside strips and/or between strips of a panel and/or between blocks of a strip and/or between modules of a block and/or between embedded components of a module.

26. The method according to claim 20, wherein the width of the groove holes is between 50 and 300 micrometers.

27. The method according to claim 20, wherein the thickness of the insulating material layers is between 40 and 240 micrometers.