PHASE CHANGE MEMORY CYCLE TIMER AND METHOD

• US 20120057401A1
• Filed: 09/08/2010
• Published: 03/08/2012
• Est. Priority Date: 09/08/2010
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: International Business Machines Corporation
• Inventors: MAFFITT, Thomas M., GABRIC, John A., LAMOREY, Mark C.
• Granted Patent: US 8,233,345 B2
• Time in Patent Office: Days
• US Class Current: 365/163
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0061 Timing circuits or methods
• CPC Class Codes: G11C 13/0064 Verifying circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0076 Write operation performed depending on read result
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

A phase change memory (PCM) cycle timer and associated method are disclosed. A system includes at least one reference phase change element (PCE). The system also includes a circuit that performs a write operation on the at least one reference PCE and substantially immediately thereafter continuously senses and returns a value of a resistance of the at least one reference PCE throughout a settling time of the at least one reference PCE.

Claims

1. A system, comprising:

at least one reference phase change element (PCE); and

a circuit that performs a write operation on the at least one reference PCE and substantially immediately thereafter continuously senses and returns a value of a resistance of the at least one reference PCE.

2. The system of claim 1, wherein the circuit senses and returns the value of the resistance of the at least one reference PCE throughout a settling time of the at least one reference PCE.

3. The system of claim 1, wherein the at least one reference PCE comprises a first reference PCE associated with a first portion of phase change memory (PCM) and a second reference PCE associated with a second portion of PCM.

4. The system of claim 3, further comprising a switching device that connects the first reference PCE to the circuit upon issuance of a write command to the first portion of PCM and connects the second reference PCE to the circuit upon issuance of a write command to the second portion of PCM.

5. The system of claim 1, wherein the circuit converts the resistance to a voltage.

6. The system of claim 5, wherein the system compares the voltage to a threshold value.

7. The system of claim 6, wherein the threshold value is based on a thermoelectric equilibrium of the at least one reference PCE.

8. The system of claim 6, wherein the system determines whether to permit or prevent writing to a portion of phase change memory associated with the at least one reference PCE based upon the comparing the voltage to the threshold value.

9. The system of claim 6, wherein, based on the comparing the voltage to the threshold value, the system holds a chip ready pin at one of a logic high state and a logic low state.

10. The system of claim 1, wherein:

the circuit comprises a write portion and a sense portion;

the write portion is electrically connected to the at least one reference PCE and the sense portion is electrically disconnected from the at least one reference PCE while performing the write operation on the at least one reference PCE; and

the write portion is electrically disconnected from the at least one reference PCE and the sense portion is electrically connected to the reference PCE while performing the sensing.

11. The system of claim 10, wherein the sense portion is electrically connected to the at least one reference PCE after the write portion is electrically disconnected from the at least one reference PCE.

12. A method, comprising:

triggering a cycle timer associated with a portion of phase change memory (PCM), wherein the triggering causes the cycle timer to;

execute a write operation on a reference phase change element (PCE) associated with the portion of PCM; and

sense a parameter of the reference PCE after the executing the write operation; and

determining whether to permit or prevent subsequent writing to the portion of PCM based upon the sensed parameter.

13. The method of claim 12, wherein the triggering occurs based on an issuance of a write command to the portion of PCM.

14. The method of claim 12, wherein the determining comprises comparing the sensed parameter to a threshold value.

15. The method of claim 14, wherein the threshold value is based on a thermoelectric equilibrium of the reference PCE.

16. The method of claim 12, wherein:

the executing the write operation comprises electrically disconnecting a sense portion of a circuit from the reference PCE and then electrically connecting a write portion of the circuit to the reference PCE; and

the sensing the parameter comprises electrically disconnecting the write portion of the circuit from the reference PCE and then electrically connecting the sense portion of the circuit to the reference PCE.

17. The method of claim 12, wherein the sensed parameter is an electrical resistance of the reference PCE.

18. The method of claim 17, wherein the sensing the parameter comprises continuously sensing the electrical resistance throughout a settling time of the reference PCE.

19. A system, comprising:

a memory controller associated with a phase change memory (PCM) array; and

a cycle timer comprising at least one reference phase change element (PCE), wherein a write command from the memory controller to a portion of the PCM array triggers the cycle timer to fill charge traps of the at least one reference PCE and thereafter continuously sense and return a value of a resistance of the at least one reference PCE.

20. The system of claim 19, wherein:

the cycle timer is separate from and operatively connected to the memory controller;

the cycle timer is operatively connected to a chip ready pin; and

the cycle timer holds the chip ready pin in a logic high state or a logic low state based on a comparison of the resistance to a threshold value.

21. The system of claim 19, wherein:

the cycle timer is integrally comprised in the memory controller; and

based on the comparison of the resistance to a threshold value, the memory controller determines whether to prevent or permit a subsequent write operation on the portion of the PCM array.