Techiniques increasing a lifetime of blocks of memory

• US 20120060060A1
• Filed: 03/07/2011
• Published: 03/08/2012
• Est. Priority Date: 11/19/2007
• Status: Active Grant

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: SandForce, Inc. (Broadcom, Inc.)
• Inventors: Danilak, Radoslav
• Granted Patent: US 8,339,881 B2
• Time in Patent Office: Days
• US Class Current: 714/37
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G06F 12/023 Free address space management
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1044 Space efficiency improvement
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G06F 3/0608 Saving storage space on storage systems
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/0631 by allocating resources to storage systems
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0649 Lifecycle management
• CPC Class Codes: G06F 3/0652 Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
• CPC Class Codes: G06F 3/0653 Monitoring storage devices or systems
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G11C 14/009 and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/26 : Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/349 : Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 : Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 17/00 : Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
• CPC Class Codes: G11C 29/04 : Detection or location of defective memory elements , e.g. cell constructio details, timing of test signals
• CPC Class Codes: G11C 29/52 : Protection of memory contents; Detection of errors in memory contents

Abstract

Techniques are described for increasing a lifetime of blocks of memory. In operation, respective life expectancy scores for each of the blocks are calculated based at least in part on a respective number of times each of the blocks is respectively erased, and further based at least in part on at least one other factor that affects the lifetime of the blocks. An order to write and recycle the blocks is determined, based at least in part on at least some of the respective lifetime expectancy scores. A total amount of the blocks that are erased and written is minimized while lifetime expectancy score variation between the blocks is equalized.

Claims

1. (canceled)

2. A method comprising:

calculating a respective lifetime expectancy score for each of a plurality of blocks of a memory based at least in part on a respective number of times each of the blocks is respectively erased and further based at least in part on at least one other factor that affects a lifetime of the blocks;

determining an order to write and recycle the blocks, based at least in part on at least some of the respective lifetime expectancy scores; and

wherein a total amount of the blocks that are erased and written is minimized while lifetime expectancy score variation between the blocks is equalized.

3. The method of claim 2, wherein the at least one other factor comprises a respective number of errors during a respective read operation involving each of the blocks.

4. The method of claim 3, wherein the errors are detected errors.

5. The method of claim 3, wherein the errors are corrected errors.

6. The method of claim 2, wherein the at least one other factor comprises a respective duration between a respective program operation and a respective read operation involving each of the blocks.

7. The method of claim 2, wherein the at least one other factor comprises a respective duration required to respectively erase each of the blocks.

8. The method of claim 2, wherein the at least one other factor comprises a respective duration required to respectively program each of the blocks.

9. The method of claim 2, wherein the at least one other factor comprises a respective number of retries required to respectively program each of the blocks.

10. The method of claim 2, wherein the at least one other factor comprises a respective number of intervening reads of a page associated with each of the blocks.

11. The method of claim 2, wherein the at least one other factor comprises a respective number of intervening reads in a neighboring page associated with each of the blocks.

12. The method of claim 2, wherein first and second ones of the blocks have respective first and second estimated lifetimes, the first estimated lifetime is longer than the second estimated lifetime, and further comprising writing the first block before writing the second block.

13. The method of claim 12, wherein the respective lifetime expectancy score for the second block is above a threshold value established for lifetime expectancy scores.

14. The method of claim 13, wherein the respective lifetime expectancy score for the first block is below the threshold value.

15. The method of claim 2, wherein the memory includes a mechanical storage device.

16. The method of claim 2, wherein the memory includes a nonvolatile memory device.

17. The method of claim 16, wherein the nonvolatile memory device includes at least one of a single-bit per cell NOR flash memory, a multi-bit per cell NOR flash memory, a single-bit per cell NAND flash memory, and a multi-bit per cell NAND flash memory.

18. The method of claim 2, further comprising storing a history of use of the blocks.

19. A tangible computer readable medium having a set of instructions stored therein which when executed by a processing element causes the processing element to perform functions comprising:

calculating a respective lifetime expectancy score for each of a plurality of blocks of a memory based at least in part on a respective number of times each of the blocks is respectively erased and further based at least in part on at least one other factor that affects a lifetime of the blocks;

determining an order to write and recycle the blocks, based at least in part on at least some of the respective lifetime expectancy scores; and

wherein a total amount of the blocks that are erased and written is minimized while lifetime expectancy score variation between the blocks is equalized.

20. The tangible computer readable medium of claim 19, wherein the at least one other factor comprises a respective number of corrected errors during a respective read operation involving each of the blocks.

21. The tangible computer readable medium of claim 19, wherein the at least one other factor comprises a respective duration between a respective program operation and a respective read operation involving each of the blocks.

22. The tangible computer readable medium of claim 19, wherein the at least one other factor comprises a respective duration required to respectively erase each of the blocks.

23. The tangible computer readable medium of claim 19, wherein the at least one other factor comprises one or more of

a respective duration required to respectively program each of the blocks, and

a respective number of retries required to respectively program each of the blocks.

24. The tangible computer readable medium of claim 19, wherein the at least one other factor comprises one or more of

a respective number of intervening reads of a page associated with each of the blocks, and

a respective number of intervening reads in a neighboring page associated with each of the blocks.

25. The tangible computer readable medium of claim 19, wherein the memory includes a nonvolatile memory device.

26. The tangible computer readable medium of claim 25, wherein the nonvolatile memory device includes at least one of a single-bit per cell NOR flash memory, a multi-bit per cell NOR flash memory, a single-bit per cell NAND flash memory, and a multi-bit per cell NAND flash memory.

27. A system comprising:

means for calculating a respective lifetime expectancy score for each of a plurality of blocks of a memory based at least in part on a respective number of times each of the blocks is respectively erased and further based at least in part on at least one other factor that affects a lifetime of the blocks;

means for determining an order to write and recycle the blocks, based at least in part on at least some of the respective lifetime expectancy scores; and

wherein a total amount of the blocks that are erased and written is minimized while lifetime expectancy score variation between the blocks is equalized.

28. The system of claim 27, wherein the at least one other factor comprises a respective number of corrected errors during a respective read operation involving each of the blocks.