MECHANISM OF FORMING SIC CRYSTALLINE ON SI SUBSTRATES TO ALLOW INTEGRATION OF GAN AND SI ELECTRONICS

• US 20120061681A1
• Filed: 09/14/2010
• Published: 03/15/2012
• Est. Priority Date: 09/14/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: TUAN, Hsiao-Chin, KALNITSKY, Alex, THEI, Kong-Beng, YU, Jiun-Lei Jerry, TSAI, Chun Lin
• Granted Patent: US 8,389,348 B2
• Time in Patent Office: Days
• US Class Current: 257/77
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/8258 the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213 , H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
• CPC Class Codes: H01L 27/0617 comprising components of the field-effect type H01L27/0251 takes precedence
• CPC Class Codes: H01L 27/085 including field-effect components only
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The mechanisms of forming SiC crystalline regions on Si substrate described above enable formation and integration of GaN-based devices and Si-based devices on a same substrate. The SiC crystalline regions are formed by implanting carbon into regions of Si substrate and then annealing the substrate. An implant-stop layer is used to cover the Si device regions during formation of the SiC crystalline regions.

Claims

1. A silicon substrate with a GaN-based device and a Si-based device on the silicon substrate, comprising:

the GaN-based device on a SiC crystalline region, wherein the SiC crystalline region is formed in the silicon substrate; and

the Si-based device on a silicon region, wherein the silicon region is next to the SiC crystalline region on the silicon substrate.

2. The silicon substrate of claim 1, wherein the surface of the SiC crystalline region is at about the same level as the surface of the silicon region.

3. The silicon substrate of claim 1, wherein the GaN-based device is selected from a group consisting of light-emitting device, power switching device, regulator, battery protector, panel display driver, and telecommunication device.

4. The silicon substrate of claim 1, wherein the GaN-based device is a metal-oxide-semiconductor high-electron-mobility-transistor (MOS-HEMT) or an HEMT.

5. The silicon substrate of claim 1, wherein the Si-based device is a MOS field effect transistor (FET).

6. The silicon substrate of claim 1, wherein the GaN-device and the Si-based device are connected to each other via interconnect.

7. The silicon substrate of claim 1, wherein there are more than one metal interconnect layers.

8. A method of forming GaN-based devices and Si-based devices on a Si substrate, comprising:

depositing an implant-stop layer over the Si substrate;

patterning the implant-stop layer to cover regions of the Si substrate and leave the remaining regions exposed;

performing ion implantation to implant carbon into the remaining regions of the Si substrate;

performing annealing to form SiC crystalline in the remaining regions;

forming the GaN-based devices on the SiC crystalline in the remaining regions and forming the Si-based devices on the covered regions of the Si substrate, wherein the implant-stop layer is removed prior to the forming of the Si-based devices.

9. The method of claim 8, wherein the ion implantation is performed at a temperature in a range from about 500°

C. to about 900°

C.

10. The method of claim 8, wherein the ion implantation is performed at a temperature in a range from about room temperature to about 150°

C.

11. The method of claim 8, wherein the annealing is performed at a temperature in a range between about 900°

C. to about 1200°

C., and the annealing is performed in an annealing equipment for a process selected from a group consisting of rapid thermal anneal, flash anneal, and laser anneal, and a furnace anneal.

12. The method of claim 8, wherein the annealing is performed at a temperature and a duration, which depend on a temperature of the ion implantation being performed.

13. The method of claim 8, wherein the dose of carbon implanted is in a range between about 1E16 ions/cm² to about 1E19 ions/cm².

14. The method of claim 8, wherein materials to make the GaN-based devices include GaN and AlGaN.

15. The method of claim 8, wherein the SiC crystalline in the remaining region has a thickness between about 1 μ

m to about 8 μ

m.

16. The method of claim 8, wherein the ion implantation is performed in multiple steps with implant energy in a range between about 20 KeV to about 800 KeV,

17. The method of claim 8, wherein the implant-stop layer is made of a dielectric material and has a thickness in a range from about 100 Å

to about 5000 Å

.

18. The method of claim 8, wherein the GaN-based device is selected from a group consisting of light-emitting device, power switching device, regulator, battery protector, panel display driver, and telecommunication device.

20. The method of claim 18, further comprising:

performing annealing to form SiC crystalline in the remaining regions after the ion implantation is performed, wherein the annealing is performed at a temperature in a range between about 900°

C. to about 1200°

C. in a rapid thermal processing system.

19. A method of forming GaN-based devices and Si-based devices on a Si substrate, comprising:

depositing an implant-stop layer over the Si substrate;

patterning the implant-stop layer to cover regions of the Si substrate and leave the remaining regions exposed;

performing ion implantation to implant carbon into the remaining regions of the Si substrate, wherein the ion implantation is performed at a temperature between about 500°

C. to about 900°

C.; and

forming the GaN-based devices on the SiC crystalline in the remaining regions and forming the Si-based devices on the covered regions of the Si substrate, wherein the implant-stop layer is removed prior to the forming of the Si-based devices.