Memory Devices For Reducing Boosting Charge Leakage And Systems Including The Same

• US 20120063235A1
• Filed: 09/09/2011
• Published: 03/15/2012
• Est. Priority Date: 09/13/2010
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Original Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Inventors: Yoon, Chi Weon, Nam, Sang-Wan, Chae, Dong Hyuk
• Granted Patent: US 9,036,425 B2
• Time in Patent Office: Days
• US Class Current: 365/185.23
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data

Abstract

A three-dimensional (3D) non-volatile memory includes a memory cell array and a merge driver configured to apply a merge voltage at the same level to a common source line and a bulk in the memory cell array.

Claims

1. A three-dimensional (3D) non-volatile memory device, comprising:

a memory cell array; and

a merge driver configured to apply a merge voltage to a common source line and a bulk in the memory cell array.

2. The 3D non-volatile memory device of claim 1, wherein the bulk includes a pocket p-type (PP) well of the memory cell array.

3. The 3D non-volatile memory device of claim 2, wherein the merge driver is configured to apply the merge voltage to the common source line and the bulk during one of a read operation, a program operation, and an erase operation.

4. The 3D non-volatile memory device of claim 3, wherein the merge driver is configured to apply a ground voltage to the common source line and the bulk during one of the read operation and the program operation.

5. The 3D non-volatile memory device of claim 3, wherein the merge driver is configured to apply an erase voltage to the common source line and the bulk during the erase operation.

6. The 3D non-volatile memory device of claim 1, further comprising:

a chip controller configured to control the merge driver.

7. The 3D non-volatile memory device of claim 1, further comprising:

a voltage generator configured to output at least one voltage to the merge driver.

8. The 3D non-volatile memory device of claim 1, wherein the 3D non-volatile memory device includes NAND flash memory.

9. The 3D non-volatile memory device of claim 1, wherein the memory cell array includes at least one cell string connected to at least one bit line;

the cell string includes a first selection transistor connected to a string selection line, a plurality of memory cells, and a second selection transistor connected to a ground selection line and the common source line; and

the merge driver is configured to apply the merge voltage to the common source line and a pocket p-type (PP) well of the memory cell array during one of a read operation, a program operation, and an erase operation.

10. A memory system, comprising:

the 3D non-volatile memory device of claim 1; and

a memory controller configured to control the 3D non-volatile memory device.

11. A memory card, comprising:

the 3D non-volatile memory device of claim 1;

a card interface; and

a controller configured to control data exchange between the card interface and the 3D non-volatile memory device.

12. A data storage system comprising:

a plurality of memory modules forming a redundant array of independent disks (RAID) array, each of the memory modules including a plurality of three-dimensional (3D) non-volatile memory devices and a memory controller configured to control operations of the 3D non-volatile memory devices, each of the 3D non-volatile memory devices including

a memory cell array, and

a merge driver configured to apply a merge voltage to a common source line and a bulk in the memory cell array; and

a RAID controller configured to control operations of the memory modules.

13. The data storage system of claim 12, wherein the bulk is a pocket p-type (PP) well of the memory cell array.

14. The data storage system of claim 13, wherein the merge driver is configured to apply the merge voltage to the common source line and the bulk during one of a read operation, a program operation, and an erase operation.

15. The data storage system of claim 14, wherein the merge driver is configured to apply a ground voltage to the common source line and the bulk during one of the read operation and the program operation.

16. A three-dimensional (3D) non-volatile memory device, comprising:

a common source line commonly connected with a device active region.

17. The 3D non-volatile memory device of claim 16, wherein the device active region includes a bulk semiconductor.

18. The 3D non-volatile memory device of claim 17, wherein the common source line and the bulk semiconductor are configured to receive a bulk voltage.

19. The 3D non-volatile memory device of claim 18, wherein the bulk voltage is applied to a pocket p-type well in the bulk semiconductor.

20. The 3D non-volatile memory device of claim 16, further comprising:

a single driver configured to apply a voltage to the commonly connected common source line and device active region.