Reordering in the Memory Controller

• US 20120072679A1
• Filed: 09/16/2010
• Published: 03/22/2012
• Est. Priority Date: 09/16/2010
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Biswas, Sukalpa, Chen, Hao
• Granted Patent: US 8,510,521 B2
• Time in Patent Office: Days
• US Class Current: 711/154
• CPC Class Codes: G06F 13/1626 by reordering requests
• CPC Class Codes: G06F 13/1642 with request queuing

Abstract

In an embodiment, a memory controller includes multiple ports. Each port may be dedicated to a different type of traffic. In an embodiment, quality of service (QoS) parameters may be defined for the traffic types, and different traffic types may have different QoS parameter definitions. The memory controller may be configured to scheduled operations received on the different ports based on the QoS parameters. In an embodiment, the memory controller may support upgrade of the QoS parameters when subsequent operations are received that have higher QoS parameters, via sideband request, and/or via aging of operations. In an embodiment, the memory controller is configured to reduce emphasis on QoS parameters and increase emphasis on memory bandwidth optimization as operations flow through the memory controller pipeline.

Claims

1. A memory controller comprising:

an agent interface unit coupled to a plurality of ports of the memory controller, wherein the agent interface unit is configured to receive memory operations and corresponding quality of service (QoS) parameters on each port; and

a plurality of memory channel units coupled to the agent interface unit, wherein the memory channel units each comprise a presorting queue and a memory interface unit to couple to a memory;

wherein the agent interface is configured to schedule memory operations from the ports to a given memory channel unit responsive to the QoS parameters of the memory operations, and wherein the agent interface units are configured to reorder memory operations to a given memory channel unit based on QoS parameters;

wherein the memory channel units are configured to group memory operations in the presorting queue according to which memory operations are expected to be performed together efficiently to the memory, and wherein the memory channel units are configured to schedule groups based on a highest level QoS parameter in each group; and

wherein the memory channel units are configured to presynthesize the memory operations into commands for the memory, and wherein the memory interface unit is configured to reorder the commands based on efficient access to the memory.

2. The memory controller as recited in claim 1 wherein the memory operations comprise read operations and write operations, and wherein the presorting queues are configured to queue read operations and write operations separately.

3. The memory controller as recited in claim 2 wherein the presorting queues are configured to eliminate QoS parameters for the write operations and to schedule between read operations and write operations responsive to a fullness of the write queues.

4. The memory controller as recited in claim 1 wherein memory operations are expected to be performed together efficiently if the memory operations are to a same page in the memory.

5. The memory controller as recited in claim 1 wherein memory operations are expected to be performed together efficiently if they are to different ranks of the memory.

6. The memory controller as recited in claim 1 wherein memory operations are expected to be performed together efficiently if they are to different banks of the memory.

7. A memory controller comprising:

an agent interface unit configured to coupled to a plurality of ports to receive memory operations and corresponding quality of service (QoS) parameters, wherein the agent interface unit is configured to transmit received memory operations to one of a plurality of memory channel units responsive to the memory channels addressed by the received memory operations and responsive to the QoS parameters of memory operations addressed to a given memory channel;

the plurality of memory channel units coupled to the agent interface unit, wherein each memory channel unit of the plurality of memory channel units is configured to schedule the memory operations received from the agent interface unit to access memory on a respective memory channel of a plurality of memory channels, wherein each memory channel unit is configured to group received memory operations into affinity groups based on efficient memory bandwidth usage among the memory operations in a given affinity group, and wherein each memory channel unit is configured to schedule the received memory operations responsive to the QoS parameters and further responsive to a size of the affinity groups.

8. The memory controller as recited in claim 7 wherein each memory operation scheduled by a given memory channel unit of the plurality of memory channel units is synthesized into one or more memory commands, and wherein the memory commands are queued by the given memory channel unit and are scheduled to a memory interface based only on efficiency of memory bandwidth usage.

9. The memory controller as recited in claim 8 wherein the plurality of memory channel units are configured to retain the QoS parameters only for read memory operations, and wherein the plurality of memory channel units are configured to queue read memory operations and write memory operations separately, and wherein each memory channel unit of the plurality of memory channel units is configured to select between read memory operations and write memory operations based on a fullness of the write queues.

10. The memory controller as recited in claim 9 wherein each memory channel unit is configured to identify a QoS level to be scheduled, and wherein each memory channel unit is configured to select a largest affinity group from a plurality of the affinity groups that include a read operation having a QoS parameter indicating the QoS level to be scheduled.

11. The memory controller as recited in claim 10 wherein each memory channel unit is configured to attempt to schedule each memory operation in the largest affinity group along with the read memory operation.

12. A system comprising:

a plurality of sources configured to transmit memory operations, each memory operation having an associated quality of service (QoS) parameter; and

a memory controller having a plurality of ports, each source of the plurality of sources configured to transmit memory operations and corresponding QoS parameters on a port of the plurality of ports, wherein a given memory operation passes through a plurality of queues in the memory controller between a given port of the plurality of ports on which the given memory operation is received and a memory interface to memory controlled by the memory controller, and wherein an importance of the QoS parameter in scheduling the given memory operation decreases as the given memory operation passes through each queue of the plurality of queues, and wherein an importance of efficiently performing the given memory operation on the memory interface increases as the memory operation passes through the plurality of queues.

13. The system as recited in claim 12 wherein a first queue of the plurality of queues is a queue for memory operations from the given port, and wherein the memory controller is configured to arbitrate among memory operations in the first queue and one or more additional queues corresponding to other ports of the plurality of ports responsive to the QoS parameters.

14. The system as recited in claim 13 wherein a second queue of the plurality queues is a queue in a memory channel unit configured to transmit memory operations on one of a plurality of memory channels, wherein the given memory operation is addressed to the one of the plurality of channels, and wherein the memory controller is configured to arbitrate among the memory operations in the second queue responsive to the QoS parameters of the memory operations and responsive to a size of one or more affinity groups of the memory operations.

15. The system as recited in claim 14 wherein the QoS parameters are dropped for write operations at the second queue, and wherein writes operations are stored in a separate queue from read operations, and wherein write operations are scheduled with respect to read operations based on a fullness of the separate queue.

16. The system as recited in claim 15 wherein the write operations are grouped into affinity groups in the separate queue and scheduling among write operations is based the size of the affinity groups.

17. The system as recited in claim 14 wherein one or more third queues of the plurality of queues comprise queues of memory commands synthesized from memory operations, wherein the memory controller is configured to synthesize the given memory operation into one or more memory commands, each memory command written to a respective one of the one or more third queues.

18. A method comprising:

receiving a plurality of memory operations on a plurality of ports of a memory controller, each memory operation having an associated quality of service (QoS) parameter;

reordering memory operations from different ones of the plurality of ports to responsive to the QoS parameters of the memory operations and further responsive to bandwidth sharing controls among the plurality of ports;

transmitting each memory operation to a memory channel of a plurality of memory channels, the memory channel corresponding to each memory operation dependent on an address of the memory operation;

writing each memory operation to either a read queue or a write queue in the memory channel unit corresponding to the memory channel, wherein the read queue is written for a read memory operation the write queue is written for a write memory operation;

sorting read memory operations in the read queue into affinity groups with other read memory operations;

reordering the read memory operations responsive to a size of the affinity groups and further responsive to the QoS parameters of the read memory operations; and

transmitting each read memory operation to a memory interface unit.

19. The method as recited in claim 18 further comprising:

sorting write memory operations into affinity groups in the write queue; and

reordering the write memory operations responsive to the size of the affinity groups and not responsive to the QoS parameters that were received on the plurality of ports with the write memory operations; and

transmitting each write memory operation to the memory interface unit.

20. The method as recited in claim 19 wherein writing the write memory operations to the write queue comprises dropping the QoS parameters of the write memory operations.

21. The method as recited in claim 19 further comprising reordering the read memory operations with the write memory operations based on a fullness of the write queue.

22. The method as recited in claim 19 further comprising:

synthesizing each memory operation received in the memory interface unit into one or more commands to be transmitted on a memory interface to a memory to performed the memory operations;

enqueuing the commands in corresponding command queues; and

scheduling the commands for transmission.