LOGIC CELL ARRAY AND BUS SYSTEM

• US 20120072699A1
• Filed: 11/04/2011
• Published: 03/22/2012
• Est. Priority Date: 10/06/2000
• Status: Active Grant

• Current Assignee: PACT XPP Schweiz AG
• Original Assignee: Dirk Reichardt, Frank Lier, Frank Mayer, Gerd Ehlers, Jens Oertel, Martin Vorbach, Nückel, Armin, Prashant Rao, Volker Baumgarte
• Inventors: VORBACH, Martin, May, Frank, Ehlers, Gerd, Nückel, Armin, Baumgarte, Volker, Oertel, Jens, Reichardt, Dirk, Lier, Frank, Rao, Prashant
• Granted Patent: US 8,471,593 B2
• Time in Patent Office: Days
• US Class Current: 712/33
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence
• CPC Class Codes: G06F 15/7825 Globally asynchronous, locally synchronous, e.g. network on chip
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 15/80 comprising an array of processing units with common control, e.g. single instruction multiple data processors G06F15/82 takes precedence ; for correlation function computation G06F17/15
• CPC Class Codes: G06F 15/8023 Two dimensional arrays, e.g. mesh, torus
• CPC Class Codes: G06F 15/8092 Array of vector units
• CPC Class Codes: G06F 15/82 data or demand driven
• CPC Class Codes: G06F 9/3001 Arithmetic instructions
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for connecting two points in order to be able to minimize the number of bus elements traversed between separate communication start and end points.

Claims

1-37. -37. (canceled)

38. A data processor on a chip comprising:

a plurality of data processing cores, each of at least some of the processing cores including;

at least one arithmetic logic unit that supports at least division and multiplication of at least 32-bit wide data; and

at least 3 registers for storing at least 32-bit wide data;

a plurality of memory units to buffer at least 32-bit wide data;

at least one interface unit for providing at least one communication channel between the data processor and external memory; and

a bus system flexibly interconnecting the plurality of processing cores, the plurality of memory units, and the at least one interface;

wherein;

the bus system includes a first structure dedicated for data transfer in a first direction and a second structure dedicated for data transfer in a second direction; and

each of at least some of the data processing cores includes a physically dedicated connection to at least one physically assigned one of the plurality of memory units, the assigned one of the plurality of memory units being accessible by another of the data processing cores via a secondary bus path of the bus system.

39. The data processor according to claim 38, wherein the at least one secondary bus path includes respective dedicated structures for each of two directions of data transfer.

40. The data processor according to any one of claims 38 and 39, wherein the at least one secondary bus path comprises at least one pipeline register for transferring data.

41. The data processor according to any one of claims 38 and 39, wherein the at least one secondary bus path comprises at least one first-in-first-out (FIFO) buffer for transferring data.

42. The data processor according to any one of claims 38 and 39, wherein the bus system supports transmission of at least 64-bit wide data.

43. The data processor according to any one of claims 38 and 39, wherein the bus system transfers data using a bus protocol.

44. The data processor according to any one of claims 38 and 39, wherein the bus system uses protocol signals for controlling the data transfer.

45. The data processor according to any one of claims 38 and 39, further comprising at least one additional data processing core whose internal architecture is different than each of the plurality of data processing cores.

46. The data processor according to claim 45, wherein the at least one additional data processing core is connectable to at least one of the plurality of memory units only via at least one secondary bus path shared with one or more of the plurality of data processing cores.

47. The data processor according to any one of claims 38 and 39, wherein the at least one interface unit includes at least two interface units, and the at least one communication channel includes a respective communication channel for each of the at least two interface units.

48. The data processor according to any one of claims 38 and 39, wherein the at least one interface unit transfers data between the data processor and external memory in packets.

49. The data processor according to any one of claims 38, 39 and 48, wherein the at least one interface unit supports a plurality of data processor internal data channels.

50. The data processor according to claim 49, wherein the at least one interface unit sorts data received from external memory to provide them to the internal channels.

51. The data processor according to any one of claims 38 and 39, wherein each of at least some of the data processing cores includes at least 8 registers for storing at least one of (a) at least 32-bit wide data and (b) at least 32-bit wide control information.

52. The data processor according to any one of claims 38 and 39, wherein each secondary bus path increases a latency of the data transmission.

53. A data processor on a chip comprising:

a plurality of data processing cores, each of at least some of the processing cores including;

at least one arithmetic logic unit that supports at least division and multiplication of at least 32-bit wide data; and

at least 3 registers for storing at least 32-bit wide data;

a plurality of memory units to buffer at least 32-bit wide data;

at least one interface unit for providing at least one communication channel between the data processor and external memory; and

a bus system flexibly interconnecting the plurality of processing cores, the plurality of memory units, and the at least one interface;

wherein;

the bus system includes a first structure dedicated for data transfer in a first direction and a second structure dedicated for data transfer in a second direction; and

each of at least some of the data processing cores includes a dedicated connection to at least one assigned one of the plurality of memory units each situated such that no other data processing core and no other memory unit is positioned between the respective data processing core and the respective assigned memory unit, the assigned one of the plurality of memory units being accessible by another of the data processing cores via a secondary bus path of the bus system.

54. The data processor according to claim 53, wherein the at least one secondary bus path includes respective dedicated structures for each of two directions of data transfer.

55. The data processor according to any one of claims 53 and 54, wherein the at least one secondary bus path comprises at least one pipeline register for transferring data.

56. The data processor according to any one of claims 53 and 54, wherein the at least one secondary bus path comprises at least one first-in-first-out (FIFO) buffer for transferring data.

57. The data processor according to any one of claims 53 and 54, wherein the bus system supports transmission of at least 64-bit wide data.

58. The data processor according to any one of claims 53 and 54, wherein the bus system transfers data using a bus protocol.

59. The data processor according to any one of claims 53 and 54, wherein the bus system uses protocol signals for controlling the data transfer.

60. The data processor according to any one of claims 53 and 54, further comprising at least one additional data processing core whose internal architecture is different than each of the plurality of data processing cores.

61. The data processor according to claim 60, wherein the at least one additional data processing core is connectable to at least one of the plurality of memory units only via at least one secondary bus path shared with one or more of the plurality of data processing cores.

62. The data processor according to any one of claims 53 and 54, wherein the at least one interface unit includes at least two interface units, and the at least one communication channel includes a respective communication channel for each of the at least two interface units.

63. The data processor according to any one of claims 53 and 54, wherein the at least one interface unit transfers data between the data processor and external memory in packets.

64. The data processor according to any one of claims 53, 54, and 63, wherein the at least one interface unit supports a plurality of data processor internal data channels.

65. The data processor according to claim 64, wherein the at least one interface unit sorts data received from external memory to provide them to the internal channels.

66. The data processor according to any one of claims 53 and 54, wherein each of at least some of the data processing cores includes at least 8 registers for storing at least one of (a) at least 32-bit wide data and (b) at least 32-bit wide control information.

67. The data processor according to any one of claims 53 and 54, wherein each secondary bus path increases a latency of the data transmission.