USE OF HASHING FUNCTION TO DISTINGUISH RANDOM AND REPEAT ERRORS IN A MEMORY SYSTEM

• US 20120072786A1
• Filed: 09/21/2010
• Published: 03/22/2012
• Est. Priority Date: 09/21/2010
• Status: Active Grant

• Current Assignee: Lenovo International Limited (Lenovo Group Ltd.)
• Original Assignee: International Business Machines Corporation
• Inventors: Bahali, Sumanta K., Dang, Tu T., Elles, Michael C., Purrington, Challis L., Scollard, Michael L., Zapata, Ivan R., Hernandez, Juan Q., Lowe, Dwayne A.
• Granted Patent: US 8,347,154 B2
• Time in Patent Office: Days
• US Class Current: 714/704
• CPC Class Codes: G06F 11/008 Reliability or availability analysis
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/076 by exceeding a count or rate limit, e.g. word- or bit count limit
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 29/42 using error correcting codes [ECC] or parity check
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair

Abstract

One embodiment provides an error detection method wherein single-bit errors in a memory module are detected and identified as being a random error or a repeat error. Each identified random error and each identified repeat error occurring in a time interval is counted. An alert is generated in response to a number of identified random errors reaching a random-error threshold or a number of identified repeat errors reaching a repeat-error threshold during the predefined interval. The repeat-error threshold is set lower than the random-error threshold. A hashing process may be applied to the memory address of each detected error to map the location of the error in the memory system to a corresponding location in an electronic table.

Claims

1. A method, comprising:

detecting single-bit errors in a memory module;

identifying each single-bit error as a random error or a repeat error;

counting each identified random error and each identified repeat error occurring in a time interval; and

generating an alert in response to a number of identified random errors reaching a random-error threshold or a number of identified repeat errors reaching a repeat-error threshold during the time interval, wherein the repeat-error threshold is lower than the random-error threshold.

2. The method of claim 1, further comprising:

identifying each first occurrence of a single-bit error among a subset of memory addresses during the time interval as a random error; and

identifying each subsequent occurrence of a single-bit error among the subset of memory addresses during the same time interval as a repeat error.

3. The method of claim 1, further comprising:

identifying the occurrence of one and only one single-bit error in a block of memory addresses during the time interval as a random error; and

identifying the occurrence of more than one single-bit error in the block of memory addresses during the time interval as a repeat error.

4. The method of claim 1, further comprising:

mapping the memory address of each detected single-bit error to a corresponding location in an electronic table;

identifying a first occurrence of a single-bit error being mapped to a location in the electronic table during the time interval as a random error; and

identifying a repeated occurrence of a single-bit error being mapped to the location in the electronic table within the time interval as a repeat error.

5. The method of claim 4, further comprising:

applying a hashing function to the memory address of each detected single-bit error to obtain the corresponding location in the electronic table.

6. The method of claim 5, wherein the hashing function maps more than one memory address to each location in the electronic table.

7. The method of claim 4, further comprising:

incrementing a count of random errors in response to each first occurrence of a detected single-bit error having been mapped to the location of the electronic table during the time interval; and

incrementing a count of repeat errors in response to a subsequent occurrence of a detected single-bit error having been mapped to the location of the electronic table during the time interval.

8. The method of claim 1, further comprising:

toggling a signature bit uniquely associated with a block of memory addresses from a first binary value to a second binary value in response to the first occurrence of a single-bit error at that block during the time interval;

incrementing a count of random errors in response to the signature bit having been toggled from the first binary value to the second binary value; and

in response to a subsequent single-bit error at that block during that same time interval, determining from the second binary value of the signature bit that at least one error has previously occurred in that block and incrementing a count of repeat errors.

9. The method of claim 1, further comprising:

separately counting the number of single-bit errors occurring at each of a plurality of blocks, each block including one or more memory addresses;

incrementing a count of random errors in response to each block having one and only one single-bit error during the time interval; and

incrementing a count of repeat errors in response to each block having more than one single-bit error during the time interval.

10. A memory system, comprising:

a memory controller including error detection control logic for detecting single-bit errors in the memory module;

a random-error counter for counting random errors occurring during a time interval;

a repeat-error counter for counting repeat errors occurring during the time interval;

a threshold comparator for comparing the random-error counter against a random-error threshold and for comparing the repeat-error counter against a repeat-error threshold, wherein the repeat-error threshold is smaller than the random-error threshold; and

an alert generator configured to generate an alert in response to the random-error counter reaching the random-error threshold or the repeat-error counter reaching the repeat-error threshold during the time interval.

11. The memory system of claim 10, further comprising:

an electronic table writeable by the memory controller, the memory controller configured for mapping the memory address of each detected single-bit error to a corresponding location in the electronic table;

control logic for identifying a first occurrence of a single-bit error being mapped to a location in the electronic table during the time interval as a random error; and

control logic identifying a repeated occurrence of a single-bit error being mapped to the location in the electronic table within the time interval as a repeat error.

12. The memory system of claim 11, further comprising:

control logic for applying a hashing function to the memory address of each detected single-bit error to obtain the corresponding location in the electronic table.

13. The memory system of claim 12, wherein the hashing function has a reduction ratio of greater than one memory address per location in the electronic table.

14. The memory system of claim 11, further comprising:

control logic for incrementing the random-error counter in response to each first occurrence of a detected single-bit error having been mapped to the location of the electronic table during the time interval; and

control logic for incrementing the repeat-error counter in response to a subsequent occurrence of a detected single-bit error having been mapped to the location during the time interval.

15. The memory system of claim 11, further comprising:

a bit uniquely associated with each location in the electronic table;

control logic for toggling each bit between first and second binary values in response to each occurrence of a detected single-bit error having been mapped to the associated location of the electronic table during the time interval;

control logic for incrementing the random-error counter in response to the bit having been toggled from the first binary value to the second binary value; and

control logic for incrementing the repeat-error counter in response to the bit having been toggled from the second binary value back to the first binary value.

16. A computer program product including computer usable program code embodied on a computer usable storage medium, the computer program product comprising:

computer usable program code for detecting single-bit errors in a memory module;

computer usable program code for identifying each single-bit error as a random error or a repeat error;

computer usable program code for counting each identified random error and each identified repeat error occurring in a time interval; and

computer usable program code for generating an alert in response to a number of identified random errors reaching a random-error threshold or a number of identified repeat errors reaching a repeat-error threshold during the time interval, wherein the repeat-error threshold is lower than the random-error threshold.

17. The computer program product of claim 16, further comprising:

computer usable program code for mapping the memory address of each detected single-bit error to a corresponding location in an electronic table;

computer usable program code for identifying a first occurrence of a single-bit error being mapped to a location in the electronic table during the time interval as a random error; and

computer usable program code for identifying a repeated occurrence of a single-bit error being mapped to the location in the electronic table within the time interval as a repeat error.

18. The computer program product of claim 17, further comprising:

computer usable program code for applying a hashing function to the memory address of each detected single-bit error to obtain the corresponding location in the electronic table.

19. The computer program product of claim 18, wherein the hashing function maps more than one memory address to each location in the electronic table.

20. The computer program product of claim 17, further comprising:

incrementing a count of random errors in response to each first occurrence of a detected single-bit error having been mapped to the location of the electronic table during the time interval; and

incrementing a count of repeat errors in response to a subsequent occurrence of a detected single-bit error having been mapped to the location of the electronic table during the time interval.