Semiconductor Devices and Methods of Manufacturing Thereof

• US 20120080686A1
• Filed: 09/30/2010
• Published: 04/05/2012
• Est. Priority Date: 09/30/2010
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Mauder, Anton, Schulze, Hans-Joachim, Timme, Hans-Joerg, Hirler, Franz, Rodriguez, Francisco Javier Santos
• Granted Patent: US 9,245,760 B2
• Time in Patent Office: Days
• US Class Current: 257/76
• CPC Class Codes: H01L 21/0237 Materials
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0245 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02513 Microstructure
• CPC Class Codes: H01L 21/02521 Materials
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/306 Chemical or electrical treatment, e.g. electrolytic etching to form insulating layers H01L21/31
• CPC Class Codes: H01L 21/30621 Vapour phase etching
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/7846 the means being located in the lateral device isolation region, e.g. STI
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

In one embodiment, a method of forming a semiconductor device includes forming a first porous semiconductor layer over a top surface of a substrate. A first epitaxial layer is formed over the first porous semiconductor layer. A circuitry is formed within and over the first epitaxial layer. The circuitry is formed without completely oxidizing the first epitaxial layer.

Claims

1. A method of forming a semiconductor device, the method comprising:

forming a first porous semiconductor layer over a top surface of a substrate;

forming a first epitaxial layer over the first porous semiconductor layer; and

forming circuitry within and over the first epitaxial layer, wherein the circuitry is formed without completely oxidizing the first epitaxial layer.

2. The method of claim 1, wherein the substrate is a silicon wafer.

3. The method of claim 1, wherein forming the first porous semiconductor layer comprises:

depositing an optional epitaxial layer; and

electrochemically etching at least a portion of the optional epitaxial layer.

4. The method of claim 3, wherein depositing the optional epitaxial layer comprises forming a first layer having a first doping, and a second layer having a second doping different from the first layer.

5. The method of claim 1, wherein forming the first porous semiconductor layer comprises:

converting a top region of the substrate into the first porous semiconductor layer by etching.

6. The method of claim 1, further comprising:

thinning the substrate from a back surface to form a thinned substrate; and

dicing the substrate to form singulated chips.

7. The method of claim 6, wherein the thinning removes the first porous semiconductor layer.

8. The method of claim 6, wherein the thinning is stopped before reaching the first porous semiconductor layer.

9. The method of claim 6, wherein the thinning exposes a surface of the first porous semiconductor layer, the method further comprising forming a back side contact by depositing a metal layer over the exposed surface of the first porous semiconductor layer.

10. The method of claim 9, further comprising converting at least a part of the first porous semiconductor layer into a metal silicide.

11. The method of claim 1, further comprising:

forming a second porous semiconductor layer between the top surface of the substrate and the first porous semiconductor layer; and

forming a second epitaxial layer between the first porous semiconductor layer and the second porous semiconductor layer.

12. The method of claim 11, further comprising:

thinning the substrate from a back surface to form a thinned substrate; and

dicing the substrate to form singulated chips.

13. The method of claim 12, wherein the thinning removes the second porous semiconductor layer, and wherein the thinning is stopped before reaching the first porous semiconductor layer.

14. The method of claim 1, further comprising forming sublayers within the first porous semiconductor layer by exposing the first porous semiconductor layer to a hydrogen anneal.

15. The method of claim 1, wherein forming a first epitaxial layer comprises exposing the first porous semiconductor layer to a hydrogen anneal.

16. The method of claim 1, wherein the substrate comprises a silicon wafer.

17. The method of claim 16, further comprising forming an epitaxial compound semiconductor layer on the first epitaxial layer.

18. The method of claim 17, wherein the epitaxial compound semiconductor layer comprises a III-V semiconductor.

19. A method of forming a semiconductor, device, the method comprising:

forming a first porous semiconductor layer over a top surface of a substrate;

forming a first epitaxial layer over the first porous semiconductor layer;

forming circuitry over the first epitaxial layer; and

thinning the substrate from a back surface to form a thinned substrate, wherein the thinning removes the first porous semiconductor layer.

20. The method of claim 19, further comprising dicing the substrate to form singulated chips.

21. The method of claim 19, wherein the substrate is a silicon wafer.

22. The method of claim 19, wherein forming the first porous semiconductor layer comprises:

depositing an optional epitaxial layer; and

electrochemically etching the optional epitaxial layer.

23. The method of claim 22, wherein depositing the optional epitaxial layer comprises forming a first layer having a first doping, and a second layer having a second doping different from the first layer.

24. The method of claim 19, further comprising:

forming a second porous semiconductor layer over the first epitaxial layer; and

forming a second epitaxial layer over the second porous semiconductor layer.

25. The method of claim 24, wherein the thinning is stopped before reaching the second porous semiconductor layer.

26. The method of claim 24, wherein forming the second porous semiconductor layer comprises:

depositing an optional epitaxial layer; and

electrochemically etching the optional epitaxial layer.

27. The method of claim 26, wherein depositing the optional epitaxial layer comprises forming a first layer having a first doping, and a second layer having a second doping different from the first layer.

28. A method of forming a semiconductor device, the method comprising:

forming a buffer semiconductor layer having pores or openings over a top surface of a substrate; and

forming a compound semiconductor layer over the buffer semiconductor layer.

29. The method of claim 28, further comprising forming an epitaxial layer between the buffer semiconductor layer and the compound semiconductor layer.

30. The method of claim 28, further comprising forming circuitry in the compound semiconductor layer.

31. The method of claim 30, wherein the circuitry comprises an optoelectronic device.

32. The method of claim 30, wherein the circuitry comprises a transistor.

33. The method of claim 28, wherein the substrate comprises a silicon wafer, and wherein the compound semiconductor layer comprises GaN.

34. The method of claim 28, wherein forming a buffer semiconductor layer comprises etching the substrate using an anodic electrochemical etch process to form a porous region.

35. The method of claim 34, wherein foaming a buffer semiconductor layer further comprises exposing the porous region to a hydrogen anneal.

36. The method of claim 28, wherein forming a buffer semiconductor layer comprises:

patterning a etch mask over the substrate using a lithographic process; and

using the etch mask, etching the openings in the substrate.

37. The method of claim 36, wherein the etching is performed using a reactive ion etch process.

38. The method of claim 36, wherein the openings are spaced uniformly on the substrate.

39. A semiconductor device comprising:

a first epitaxial layer disposed within a substrate;

circuitry disposed within and over the first epitaxial layer, the circuitry disposed proximate to a top surface of the substrate; and

a first porous layer disposed on a back surface of a substrate, the back surface being opposite to the top surface, wherein the first porous layer comprises a metal silicide.

40. The device of claim 39, further comprising:

a second porous layer disposed over the first pbrous layer, the second porous layer comprising porous semiconductor.

41. The device of claim 39, further comprising:

back side contacts coupled to the first porous layer.

42. A semiconductor device comprising:

a buffer semiconductor layer having pores or openings disposed over a top surface of a substrate; and

a compound semiconductor layer disposed over the buffer semiconductor layer.

43. The device of claim 42, wherein the openings are trenches.

44. The device of claim 42, wherein the openings are patterned holes.

45. The device of claim 42, wherein the pores are randomly distributed within the buffer semiconductor layer.

46. The device of claim 42, wherein the substrate comprises a silicon wafer, and wherein the compound semiconductor layer comprises an III-V semiconductor.

47. The device of claim 42, wherein the substrate comprises a silicon wafer, and wherein the compound semiconductor layer comprises GaN.

48. The device of claim 42, further comprising an epitaxial layer disposed between the buffer semiconductor layer and the compound semiconductor layer.

49. The device of claim 48, wherein the substrate comprises a silicon wafer, wherein the epitaxial layer is a silicon layer, and wherein the compound semiconductor layer comprises GaN.

50. The device of claim 49, wherein the GaN is aligned to a (110) surface of the epitaxial layer.

51. The device of claim 42, further comprising device regions disposed in the compound semiconductor layer.