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TESTING METHOD FOR SEMICONDUCTOR INTEGRATED ELECTRONIC DEVICES AND CORRESPONDING TEST ARCHITECTURE

  • US 20120081137A1
  • Filed: 10/04/2011
  • Published: 04/05/2012
  • Est. Priority Date: 10/05/2010
  • Status: Active Grant
First Claim
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1. A method, comprising:

  • testing a device having an integrated testing circuit using a tester, the testing including;

    sending at least some of messages, instructions, test signals, and information exclusively from said tester to said device without sending any messages, instructions, test signals, and information from the device to the testing circuit.

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